US 11,699,489 B2 · Nonvolatile memory device and method of programming in the same

Abstract

In a method of programming in a nonvolatile memory device including a memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, wherein the peripheral circuit region is vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory block in the memory cell region including a plurality of stacks disposed in a vertical direction is provided where the memory block includes cell strings each of which includes memory cells connected in series in the vertical direction between a source line and each of bitlines. A plurality of intermediate switching transistors disposed in a boundary portion between two adjacent stacks in the vertical direction is provided, where the intermediate switching transistors perform a switching operation to control electrical connection of the cell strings, respectively. A boosting operation is performed to boost voltages of channels of the plurality of stacks while controlling the switching operation of the intermediate switching transistors during a program operation with respect to the memory block. Program voltage disturbance and pass voltage disturbance are reduced through control of the switching operation of the intermediate switching transistors.

Claims22

Dependent claims

A method of programming a memory block comprising a plurality of stacks connected in series in a vertical direction by forming a plurality of cell strings between a plurality of bitlines and a source line, the method comprising:

determining, from among the plurality of stacks, a selected stack comprising memory cells to be programmed according to a program command, the selected stack being separated from an erased stack comprising non-programmed memory cells by a boundary portion comprising a plurality of intermediate switching transistors;
during a first boosting period, applying a turn-on voltage to gate electrodes of the plurality of intermediate switching transistors;
during the first boosting period, applying a first pass voltage to wordlines of the erased stack;
during a second boosting period after the first boosting period, applying a turn-off voltage to the gate electrodes of the plurality of intermediate switching transistors;
during the second boosting period, applying a second pass voltage to wordlines of the selected stack;
and
during a program execution period after the second boosting period, applying a program voltage to a selected wordline of the selected stack.

4 more elements

A memory device comprising:

a memory block comprising a plurality of stacks connected in series in a vertical direction by forming a plurality of cell strings between a plurality of bitlines and a source line;
and
a control circuit configured to:
determine, from among the plurality of stacks, a selected stack comprising memory cells to be programmed according to a program command, the selected stack being separated from an erased stack comprising non-programmed memory cells by a boundary portion comprising a plurality of intermediate switching transistors;
during a first boosting period, apply a turn-on voltage to gate electrodes of the plurality of intermediate switching transistors;
during the first boosting period, apply a first pass voltage to wordlines of the erased stack;
during a second boosting period after the first boosting period, apply a turn-off voltage to the gate electrodes of the plurality of intermediate switching transistors;
during the second boosting period, apply a second pass voltage to wordlines of the selected stack;
and
during a program execution period after the second boosting period, apply a program voltage to a selected wordline of the selected stack.

7 more elements

A system comprising:

a memory device and a memory controller configured to control the memory device, the memory device comprising:
a memory block comprising a plurality of stacks connected in series in a vertical direction by forming a plurality of cell strings between a plurality of bitlines and a source line;
and
a control circuit configured to:
determine, from among the plurality of stacks, a selected stack comprising memory cells to be programmed according to a program command received from the memory controller, the selected stack being separated from an erased stack comprising non-programmed memory cells by a boundary portion comprising a plurality of intermediate switching transistors;
during a first boosting period, apply a turn-on voltage to gate electrodes of the plurality of intermediate switching transistors;
during the first boosting period, apply a first pass voltage to wordlines of the erased stack;
during a second boosting period after the first boosting period, apply a turn-off voltage to the gate electrodes of the plurality of intermediate switching transistors;
during the second boosting period, apply a second pass voltage to wordlines of the selected stack;
and
during a program execution period after the second boosting period, apply a program voltage to a selected wordline of the selected stack.

8 more elements

Dependencies are inferred from the claim text.

Nonvolatile memory device and method of programming in the same

Life of this patent

Nonvolatile memory device and method of programming in the same

Life of this patent

Abstract

Claims22