Device-region layout for embedded flash

An integrated chip comprising:

• a substrate;
• a pair of erase gates over the substrate;
• a pair of control gates over the substrate, wherein the control gates are between and respectively border the erase gates;
• a pair of word lines over the substrate, wherein the word lines are between and respectively border the control gates;
• a source/drain region in the substrate, wherein the source/drain region is between and borders the word lines;
• and
• a trench isolation structure in the substrate and extending in a closed path around the source/drain region, wherein the closed path is localized between the control gates.

An integrated chip comprising:

• a substrate;
• and
• an erase gate, a control gate, and a word line overlying the substrate and laterally elongated in parallel in a first direction, wherein the control gate is between and borders the erase gate and the word line, and wherein the control gate and the word line respectively have a control-gate sidewall and a word-line sidewall facing away from the erase gate;
• wherein the substrate has a substrate sidewall that faces in a second direction transverse to the first direction and that is laterally offset from and between the word-line and control-gate sidewalls, and wherein the second direction extends away from the erase gate.