Semiconductor memory device to hold 5-bits of data per memory cell
AssigneeKioxia Corporation
InventorsTomonori Takahashi, Masanobu Shirakawa, Osamu Torii, Marie Takada
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AssigneeKioxia Corporation
InventorsTomonori Takahashi, Masanobu Shirakawa, Osamu Torii, Marie Takada
Estimating the term…
According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.
A semiconductor memory device comprising:
A semiconductor memory device comprising:
Dependencies are inferred from the claim text.