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US 11,699,484 B2Granted
Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers
AssigneeZeno Semiconductor, Inc.
InventorsBenjamin S. Louie, Yuniarto Widjaja, Zvi Or-Bach
Life of this patent
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Abstract
A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.
Claims18
An integrated circuit comprising:
- a semiconductor memory array comprising a plurality of floating body memory cells, each of said floating body memory cells comprising:
- a floating body region configured to be charged to a level indicative of a state of the floating body memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types;
- a first region in electrical contact with said floating body region, said first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;
- a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having said first conductivity type;
- a first transistor connected to said second region of said floating body memory cell;
- a second transistor connected to said first transistor;
- and
- circuits configured to perform read and write operations on said semiconductor memory array.
5 more elements
An integrated circuit comprising:
- a semiconductor memory array comprising a plurality of floating body memory cells, each said floating body memory cell comprising:
- a floating body region configured to be charged to a level indicative of a state of the floating body memory cell, said floating body region having a first conductivity type selected from p-type and n-type conductivity types;
- a first region in electrical contact with said floating body region, said first region having a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;
- a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having said first conductivity type;
- a pull down device having a gate electrically connected to said second region;
- a select device electrically connected to said pull down device, said select device being configured to be connected to a read bit line;
- and
- circuits configured to perform read and write operations on said semiconductor memory array.
5 more elements
Dependencies are inferred from the claim text.