Memory system with burst mode having logic gates as sense elements

A memory system comprising:

• a first memory array including a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline;
• a second memory array including a third set of memory cells coupled to a second inner wordline and a fourth set of memory cells coupled to a second outer wordline;
• a plurality of sense elements coupled to a plurality of columns such that each of the plurality of columns has a corresponding sense element, wherein the plurality of columns is coupled to a shared column multiplexer, and wherein each of the plurality of sense elements comprises a plurality of inverters coupled in series between an output data latch and the shared column multiplexer;
• and
• a control unit configured to generate control signals for:
• in response to a burst mode read request, simultaneously:
• (1) asserting a first wordline signal on the first inner wordline coupled to each of a first plurality of inner bitlines, (2) asserting a second wordline signal on the first outer wordline coupled to each of a first plurality of outer bitlines, wherein each of the first plurality of outer bitlines includes a first portion configured to fly over or fly under a corresponding inner bitline (3) asserting a third wordline signal on the second inner wordline coupled to each of a second plurality of inner bitlines, and (4) asserting a fourth wordline signal on the second outer wordline coupled to each of a second plurality of outer bitlines, wherein each of the second plurality of outer bitlines includes a second portion configured to fly over or fly under a corresponding inner bitline, and
• as part of a burst, outputting data into the output data latch corresponding to a subset of each of the first set of memory cells, the second set of memory cells, the third set of memory cells, and the fourth set of memory cells sensed by a selected set of the plurality of sense elements corresponding to a selected set of the plurality of columns.

A memory system comprising:

• a first memory sub-array and a second memory sub-array, wherein the first memory sub-array includes a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline, wherein the second memory sub-array includes a third set of memory cells coupled to a second inner wordline and a fourth set of memory cells coupled to a second outer wordline, wherein each of the first set of memory cells and the second set of memory cells is organized in a first plurality of columns, and wherein each of the third set of memory cells and the fourth set of memory cells is organized in a second plurality of columns;
• a plurality of sense elements coupled to a plurality of columns such that each of the plurality of columns has a corresponding sense element, wherein the plurality of columns is coupled to a shared column multiplexer, and wherein each of the plurality of sense elements comprises a plurality of inverters coupled in series between an output data latch and the shared column multiplexer;
• and
• a control unit configured to generate control signals both for:
• in a first burst mode, in response to a first burst mode read request, simultaneously:
• (1) asserting a first wordline signal on the first inner wordline coupled to each of a first plurality of inner bitlines, (2) asserting a second wordline signal on the first outer wordline coupled to each of a first plurality of outer bitlines, wherein each of the first plurality of outer bitlines includes a first portion configured to fly over or fly under a corresponding inner bitline, (3) asserting a third wordline signal on the second inner wordline coupled to each of a second plurality of inner bitlines, (4) asserting a fourth wordline signal on the second outer wordline coupled to each of a second plurality of outer bitlines, wherein each of the second plurality of outer bitlines includes a second portion configured to fly over or fly under a corresponding inner bitline, and using the shared column circuitry, and outputting data into the output data latch from each of the first set of memory cells, the second set of memory cells, the third set of memory cells, and the fourth set of memory cells as part of a burst, and
• in a second burst mode, in response to a second burst mode read request, simultaneously:
• (1) asserting a first wordline signal on the first inner wordline coupled to each of a first plurality of inner bitlines, and (2) asserting a second wordline signal on the first outer wordline coupled to each of a first plurality of outer bitlines, wherein each of the first plurality of outer bitlines includes a first portion configured to fly over or fly under a corresponding inner bitline, and outputting data into the output data latch from each of the first set of memory cells and the second set of memory cells.