Analog in-memory computing based inference accelerator

A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, comprising:

• a set of input connectors for receiving a corresponding set of modulated input signals (A+, A−) representative of a sign and a magnitude of the digital data input;
• a memory unit configured for storing the balanced ternary weight;
• and
• a logic unit connected to the set of input connectors and the memory unit to receive the data input and the balanced ternary weight, the logic unit configured to:
• selectively enable one of a plurality of conductive paths for supplying a first charge to a read bit line (S;
• S+, S−) during a duty cycle of the set of input signals if the data input and the balanced ternary weight both have a positive sign or both have a negative sign, selectively enable a different one of the plurality of conductive paths for supplying a second charge to the same one read bit line (S), or to a different one read bit line (S+, S−), during the duty cycle if the data input and the balanced ternary weight have opposite signs, and disable each of the plurality of conductive paths if at least one of the group consisting of the balanced ternary weight and the data input has zero magnitude, in order to prevent any supply of charges to the one or more read bit lines, wherein the duty cycle is indicative of the data input magnitude, and wherein a ratio of the first to the second charge is negative one if the first and second charge are supplied to a same read bit line, and positive one if the first and second charge are supplied to different read bit lines,
• wherein the set of input connectors comprises a first and a second single-ended input connector for receiving a modulated first and second input signal (/A+, /A−), and wherein the logic unit further comprises:
• a first and a second output (OUT+, OUT−) connectable to respective ones of a differential pair of read bit lines (S+, S−);
• a first transistor connected between the first output (OUT+) and the first input connector and having a gate electrode connected to the memory unit to receive a first one (W+) of a set of binary-valued weight signals encoding the balanced ternary weight, for selectively enabling a first conductive path if the data input and the balanced ternary weight both have positive sign;
• a second transistor connected between the first output and the second input connector and having a gate electrode connected to the memory unit to receive a second one (W−) of the set of binary-valued weight signals encoding the balanced ternary weight, for selectively enabling a second conductive path if the data input and the balanced ternary weight both have negative sign;
• a third transistor connected between the second output (OUT−) and the first input connector and having a gate electrode connected to the memory unit to receive the second binary-valued weight signal (W−), for selectively enabling a third conductive path if the data input has positive sign and the balanced ternary weight has negative sign;
• and
• a fourth transistor connected between the second output (OUT−) and the second input connector and having a gate electrode connected to the memory unit to receive the first binary-valued weight signal (W+), for selectively enabling a fourth conductive path if the data input has negative sign and the balanced ternary weight has positive sign.

A compute cell for in-memory multiplication of a digital data input and a balanced ternary weight, comprising:

• a set of input connectors for receiving a corresponding set of modulated input signals (A+, A−) representative of a sign and a magnitude of the digital data input;
• a memory unit configured for storing the balanced ternary weight;
• and
• a logic unit connected to the set of input connectors and the memory unit to receive the data input and the balanced ternary weight, the logic unit configured to:
• selectively enable one of a plurality of conductive paths for supplying a first charge to a read bit line (S;
• S+, S−) during a duty cycle of the set of input signals if the data input and the balanced ternary weight both have a positive sign or both have a negative sign, selectively enable a different one of the plurality of conductive paths for supplying a second charge to the same one read bit line (S), or to a different one read bit line (S+, S−), during the duty cycle if the data input and the balanced ternary weight have opposite signs, and disable each of the plurality of conductive paths if at least one of the group consisting of the balanced ternary weight and the data input has zero magnitude, in order to prevent any supply of charges to the one or more read bit lines, wherein the duty cycle is indicative of the data input magnitude, and wherein a ratio of the first to the second charge is negative one if the first and second charge are supplied to a same read bit line, and positive one if the first and second charge are supplied to different read bit lines,
• wherein the set of input connectors comprises a pair of complementary input connectors for receiving a modulated input signal (A) and its complement (/A), and wherein the logic unit further comprises:
• an output (OUT) connectable to a read bit line (S);
• a first transistor of a first conductivity type having a drain electrode connected to the output (OUT), a source electrode connected to a first one of the pair of complementary input connectors to receive the input signal (A), and a gate electrode connected to the memory unit to receive a first one (/W+) of a set of binary-valued weight signals encoding the balanced ternary weight, for selectively enabling a first conductive path if the data input and the balanced ternary weight both have positive sign;
• and
• a second transistor of a second conductivity type, opposite to the first conductivity type, having a drain electrode connected to the output (OUT), a source electrode connected to a second one of the pair of complementary input connectors to receive the complement of the input signal (/A), and a gate electrode connected to the memory unit to receive a second one (W−) of the set of binary-valued weight signals, for selectively enabling a second conductive path if the data input has positive sign and the balanced ternary weight both has negative sign.