Semiconductor memory device including word line and bit line
AssigneeSK hynix Inc.
InventorKee Teok Park
Life of this patent
Estimating the term…
Abstract
A stacked memory device includes a plurality of lower word lines extending in a first direction, a bit line positioned over the plurality of the lower word lines and extending in a second direction intersecting with the first direction, and a plurality of upper word lines positioned over the bit line and extending in the first direction. The stacked memory device also includes a plurality of lower memory cells including a lower capacitor and a lower switching element between the lower word lines and the bit line. The stacked memory device further includes a plurality of upper memory cells including an upper capacitor and an upper switching element between the bit line and the upper word lines.
Claims18
A memory device, comprising:
- a first bit line and a second bit line which are arranged in parallel on a first plane;
- a lower word line arranged to intersect the first and the second bit lines to form lower memory cells, the lower word line arranged in a second plane located below the first plane on which the first and second bit lines are arranged;
- and
- an upper word line arranged to intersect the first and the second bit lines to form upper memory cells, the upper word line arranged in a third plane located above the first plane,
- wherein the first bit line is spaced apart from the lower word line by a first distance at an intersection of the first bit line and the lower word line, and
- wherein the first bit line is spaced apart from the upper word line by a second distance different from the first distance at an intersection of the first bit line and the upper word line.
A memory device, comprising:
- a word line arranged over a substrate;
- a first bit line arranged over the word line to intersect the word line, the first bit line together with the word line to form a first memory cell;
- and
- a second bit line arranged over the word line to intersect the word line, the second bit line being parallel to the first bit line and the second bit line together with the word line to form a second memory cell,
- wherein the word line is spaced apart from the substrate by a first height and the first and second bit lines are spaced apart from the substrate by a second height different from the first height, and
- wherein the word line is spaced apart from the first bit line by a first distance at an intersection of the word line and the first bit line, and the word line is spaced apart from the second bit line by a second distance different from the first distance at an intersection of the word line and the second bit line.
A memory device, comprising:
- a first bit line and a second bit line which are arranged in parallel on a same plane;
- a lower word line arranged below the first and the second bit lines to intersect the first and the second bit lines, and arranged closest to the first and second bit lines in a lower direction;
- and
- an upper word line arranged on the first and the second bit lines to intersect the first and the second bit lines, and arranged closest to the first and second bit lines in an upper direction,
- wherein the first bit line is spaced apart from the lower word line by a first distance at an intersection of the first bit line and the lower word line, and the first bit line is spaced apart from the upper word line by a second distance different from the first distance at an intersection of the first bit line and the upper word line.
Dependencies are inferred from the claim text.