Semiconductor memory device with column path control circuit that controls column path for accessing a core circuit with multiple bank groups and column path control circuit therefor
AssigneeSK hynix Inc.
InventorJi Eun Kim
Life of this patent
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Abstract
A semiconductor memory device may include a core circuit including a plurality of memory cell arrays electrically connected between a plurality of row lines and a plurality of column lines, and a column path control circuit configured to generate a preliminary column pulse from a command signal irrelevant to a column address signal, to generate a main column pulse in response to an enable time point of the column address signal and an enable time point of the preliminary column pulse, and to enable an access target column line among the plurality of column lines.
Claims15
A semiconductor memory device comprising:
- a core circuit including a plurality of memory cell arrays electrically connected between a plurality of row lines and a plurality of column lines;
- and
- a column path control circuit configured to generate a preliminary column pulse from a command signal irrelevant to a column address signal, to generate a main column pulse in response to an enable time point of the column address signal and an enable time point of the preliminary column pulse, and to enable an access target column line among the plurality of column lines.
A semiconductor memory device comprising:
- a core circuit including a plurality of memory cell arrays electrically connected between a plurality of row lines and a plurality of column lines, wherein the plurality of memory cell arrays are divided into a plurality of bank groups;
- and
- a column path control circuit controlling a column path for accessing an access target column line among the plurality of column lines,
- wherein the column path control circuit comprises:
- a preliminary column pulse generation circuit shared among the plurality of memory bank groups and configured to generate a preliminary column pulse by delaying a command signal during a first period of time;
- an address processing circuit shared among the plurality of memory bank groups and configured to determine a first time point and a second time point, the first time point determined based on the command signal and a bank group address signal, and the second time point determined based on the preliminary column pulse and a delayed bank group address signal;
- and
- an addressing pulse generation circuit provided for each of the plurality of bank groups and configured to generate a main column pulse that is activated between the first time point and the second time point and to provide the main column pulse to the access target column line,
- wherein the address processing circuit comprises:
- a first decoder configured to decode the bank group address signal and generate a set signal, which determines the first time point at a time point at which the command signal is enabled;
- and
- a second decoder configured to decode the delayed bank group address signal during the first period of time and generate a reset signal, which determines the second time point at a time point at which the preliminary column pulse is enabled.
A column path control circuit that controls a column path for accessing a core circuit including a plurality of memory cells electrically connected between a plurality of row lines and a plurality of column lines, the column path control circuit comprising:
- a column enable signal generation circuit configured to generate a preliminary column pulse from a command signal irrelevant to a column address signal, and to generate a main column pulse in response to an enable time point of the column address signal and an enable time point of the preliminary column pulse;
- and
- a column selection signal generation circuit configured to generate a column selection signal on the basis of the main column pulse and to enable an access target column line among the plurality of column lines.
Dependencies are inferred from the claim text.