Semiconductor memory device in which data writing to cells is controlled using program pulses

A semiconductor memory device comprising:

• a source line extending in a first direction and a second direction intersecting the first direction:
• a first semiconductor pillar having a first semiconductor layer extending in a third direction intersecting the first direction and the second direction and electrically connected to the source line;
• a second semiconductor pillar having a second semiconductor layer extending in the third direction and electrically connected to the source line;
• i first word lines (i is an integer of 4 or more) stacked in the third direction;
• i second word lines stacked in the third direction and having the same positions as the i first word lines with respect to the third direction, respectively;
• and
• a driver, wherein
• the first semiconductor pillar has a first string provided on a first side and a second string provided on a second side,
• the first string has i first memory cells,
• the i first memory cells are electrically connected in series, arranged along the third direction, and connected to the i first word lines, respectively,
• the second string has i second memory cells,
• the i second memory cells are electrically connected in series, arranged along the third direction, and connected to the i second word lines, respectively,
• the second semiconductor pillar has a third string provided on a third side and a fourth string provided on a fourth side,
• the third string has i third memory cells,
• the i third memory cells are electrically connected in series, arranged along the third direction, and connected to the i first word lines, respectively,
• the fourth string has i fourth memory cells,
• the i fourth memory cells are electrically connected in series, arranged along the third direction, and connected to the i second word lines, respectively,
• a position of the first of the first word line of the i first word lines is closest to a position of the source line, and a position of the i-th of the first word line of the i first word lines is farthest from the position of the source line,
• a position of the first of the second word line of the i second word lines is closest to the position of the source line, and the position of the i-th of the second word line of the i second word lines is farthest from the position of the source line,
• the i first memory cells and the i second memory cells share the first semiconductor layer,
• the i third memory cells and the i fourth memory cells share the second semiconductor layer,
• in writing data to the k-th (k is an integer smaller than i and greater than 1) first memory cell, in a first operation of the writing operation, the driver supplies the k-th first word line with a first voltage larger than a reference voltage, and supplies the k-th second word line with a second voltage smaller than the reference voltage,
• the first semiconductor pillar is electrically connected to a first bit line,
• the second semiconductor pillar is electrically connected to a second bit line,
• in the first operation, the driver supplies the reference voltage to the first bit line and the second bit line, and raises the voltage of a second bit line from the reference voltage to a third voltage larger than the reference voltage, and
• in the first operation,
• the driver supplies the first voltage to the first word line other than a k-th first word line and a k-1-th or lower of the second word line, and supplies the second voltage to the second word line of k+1-th or higher of the second word line,
• a k-th or higher of the first memory cell and a k-th or higher of the third memory cell are turned on, and
• a k-th or higher of the second memory cell and a k-th or higher of the fourth memory cell are turned off.

A semiconductor memory device comprising:

• a source line extending in a first direction and a second direction intersecting the first direction;
• a first semiconductor pillar having a first semiconductor layer extending in a third direction intersecting the first direction and the second direction and electrically connected to the source line;
• a second semiconductor pillar having a second semiconductor layer extending in the third direction and electrically connected to the source line;
• i first word lines (i is an integer of 4 or more) stacked in the third direction;
• i second word lines stacked in the third direction and having the same positions as the i first word lines with respect to the third direction, respectively;
• and
• a driver, wherein
• the first semiconductor pillar has a first string provided on a first side and a second string provided on a second side,
• the first string has i first memory cells,
• the i first memory cells are electrically connected in series, arranged along the third direction, and connected to the i first word lines, respectively,
• the second string has i second memory cells,
• the i second memory cells are electrically connected in series, arranged along the third direction, and connected to the i second word lines, respectively,
• the second semiconductor pillar has a third string provided on a third side and a fourth string provided on a fourth side,
• the third string has i third memory cells,
• the i third memory cells are electrically connected in series, arranged along the third direction, and connected to the i first word lines, respectively,
• the fourth string has i fourth memory cells,
• the i fourth memory cells are electrically connected in series, arranged along the third direction, and connected to the i second word lines, respectively,
• a position of the first of the first word line of the i first word lines is closest to a position of the source line, and a position of the i-th of the first word line of the i first word lines is farthest from the position of the source line,
• a position of the first of the second word line of the i second word lines is closest to the position of the source line, and the position of the i-th of the second word line of the i second word lines is farthest from the position of the source line,
• the i first memory cells and the i second memory cells share the first semiconductor layer,
• the i third memory cells and the i fourth memory cells share the second semiconductor layer,
• in writing data to the k-th (k is an integer smaller than i and greater than 1) first memory cell, in a first operation of the writing operation, the driver supplies the k-th first word line with a first voltage larger than a reference voltage, and supplies the k-th second word line with a second voltage smaller than the reference voltage,
• the first semiconductor pillar is electrically connected to a first bit line,
• the second semiconductor pillar is electrically connected to a second bit line,
• in the first operation, the driver supplies the reference voltage to the first bit line and the second bit line, and raises the voltage of a second bit line from the reference voltage to a third voltage larger than the reference voltage, and
• in the first operation,
• the driver supplies the first voltage to the first word line other than a k-th first word line and a k-2-th or lower of the second word line, and supplies a k-1-th or higher of the second word line,
• a k-th or higher of the first memory cell and a k-th or higher of the third memory cell are turned on, and
• a k-th or higher of the second memory cell and a k-th or higher of the fourth memory cell are turned off.

A semiconductor memory device comprising:

• a source line extending in a first direction and a second direction intersecting the first direction;
• a first semiconductor pillar having a first semiconductor layer extending in a third direction intersecting the first direction and the second direction and electrically connected to the source line;
• a second semiconductor pillar having a second semiconductor layer extending in the third direction and electrically connected to the source line;
• i first word lines (i is an integer of 4 or more) stacked in the third direction;
• i second word lines stacked in the third direction and having the same positions as the i first word lines with respect to the third direction, respectively;
• and
• a driver, wherein
• the first semiconductor pillar has a first string provided on a first side and a second string provided on a second side,
• the first string has i first memory cells,
• the i first memory cells are electrically connected in series, arranged along the third direction, and connected to the i first word lines, respectively,
• the second string has i second memory cells,
• the i second memory cells are electrically connected in series, arranged along the third direction, and connected to the i second word lines, respectively,
• the second semiconductor pillar has a third string provided on a third side and a fourth string provided on a fourth side,
• the third string has i third memory cells,
• the i third memory cells are electrically connected in series, arranged along the third direction, and connected to the i first word lines, respectively,
• the fourth string has i fourth memory cells,
• the i fourth memory cells are electrically connected in series, arranged along the third direction, and connected to the i second word lines, respectively,
• a position of the first of the first word line of the i first word lines is closest to a position of the source line, and a position of the i-th of the first word line of the i first word lines is farthest from the position of the source line,
• a position of the first of the second word line of the i second word lines is closest to the position of the source line, and the position of the i-th of the second word line of the i second word lines is farthest from the position of the source line,
• the i first memory cells and the i second memory cells share the first semiconductor layer,
• the i third memory cells and the i fourth memory cells share the second semiconductor layer,
• in writing data to the k-th (k is an integer smaller than i and greater than 1) first memory cell, in a first operation of the writing operation, the driver supplies the k-th first word line with a first voltage larger than a reference voltage, and supplies the k-th second word line with a second voltage smaller than the reference voltage,
• the first semiconductor pillar and the second semiconductor pillar are electrically connected to the source line,
• in the first operation, the driver raises the voltage of a second bit line from the reference voltage to a third voltage larger than the reference voltage, and
• in the first operation,
• the driver supplies the first voltage to the k-th or lower of the first word line, and supplies the second voltage to the k-th or lower of the second word line,
• the k-th or lower of the first memory cell and the k-th or lower of the third memory cell are turned on, and
• the k-th or lower of the second memory cell and the k-th or lower of the fourth memory cell are turned off.