US 11,699,472 B2 · Semiconductor memory device and memory system including the same

Abstract

A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

Drawings

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Drawings

Claims20

Dependent claims

A semiconductor memory device comprising:

a data clock buffer configured to generate first through fourth clock signals based on a data clock signal received from a memory controller;
a quadrature error correction circuit configured to receive the first through fourth clock signals, configured to perform a locking operation to generate a first corrected clock signal and a second corrected clock signal which have a phase difference of 90 degrees with respect to each other by adjusting at least one of a skew and a duty error of at least some of the first through fourth clock signals in a first operation mode based on an initialization command and configured to perform a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal in a second operation mode;
a clock generation circuit configured to generate an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal;
and
a data input/output (I/O) buffer configured to generate a data signal by sampling data from a memory cell array based on the output clock signal and configured to transmit the data signal and the strobe signal to the memory controller.

2 more elements

Dependencies are inferred from the claim text.

Description12,732 words

Summary1,048 words

#This application claims the benefit of priority under 35 USC § 119 to Korean Patent Application No. 10-2021-0051584, filed on Apr. 21, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.

#The present disclosure relates to memories, and more particularly to semiconductor memory devices to perform relocking operation of a quadrature error correction circuit and memory systems including the same.

#A semiconductor memory device may be classified as a volatile memory device or a nonvolatile memory device. A volatile memory device refers to a memory device that loses data stored therein at power-off. As an example of a volatile memory device, a dynamic random access memory (DRAM) may be used in various devices such as a mobile system, a server, or a graphic device.

Brief description of the drawings30 figures

#Example embodiments will be described below in more detail with reference to the accompanying drawings.

#FIG. 1 is a block diagram illustrating a memory system according to example embodiments.

#FIG. 2 is a block diagram illustrating the semiconductor memory device in FIG. 1 according to example embodiments.

Detailed description11,029 words

#Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown.

#FIG. 1 is a block diagram illustrating a memory system 20 according to example embodiments.

#Referring to FIG. 1, the memory system 20 may include a memory controller 100 and a semiconductor memory device 200.

Facts

Application

17/526,398Filed 15 Nov 2021

Priority

KR 10-2021-005158421 Apr 2021

Published

US 2022/0343957 A127 Oct 2022

Granted

11 Jul 2023

Term ends

15 Nov 2041

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification15 codes

G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
G11C 29/023
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in clock generator or timing circuitry
G11C 7/1057
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output…
G11C 7/1084
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input buffers,…

Timeline

21 Apr 2021Priority claimedKR 10-2021-0051584
15 Nov 2021Application filedUS 17/526,398
22 Nov 2021Assigned to Samsung Electronics Co., Ltd.assignment of assignor's interest
27 Oct 2022PublishedUS 2022/0343957 A1
11 Jul 2023GrantedUS 11,699,472 B2
12 Oct 2026TodayWithin its term
15 Nov 2041Term endsEstimated

Semiconductor memory device and memory system including the same

Life of this patent

Semiconductor memory device and memory system including the same

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims20

Description12,732 words

Drawings

Classification15 codes

Life of this patent

Description12,732 words