Synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM) having increased per data pin bandwidth

A computing system, comprising:

• a plurality of processing cores;
• a network interface;
• a memory controller coupled to the plurality of processing cores;
• a data bus coupled to the memory controller;
• a memory module coupled to the data bus, the memory module comprising either of a) and b) below:
• a) first logic circuitry to multiplex on a data bus a first data burst, a second data burst, a third data burst and a fourth data burst having different respective base target addresses that respectively target a first memory rank, a second memory rank, a third memory rank and a fourth memory rank, wherein, a first data transfer for the first data burst occurs on a first edge of a first pulse of a data strobe signal for the data bus and a second data transfer for the second data burst occurs on a second edge of the first pulse of the data strobe signal, and wherein, a third data transfer for the third data burst occurs on a first edge of a second pulse of the data strobe signal for the data bus and a fourth data transfer for the fourth data burst occurs on a second edge of the second pulse, wherein the second pulse immediately follows the first pulse on the data strobe signal;
• and,
• b) second logic circuitry to multiplex on a data bus a first data burst, a second data burst, a third data burst and a fourth data burst having different respective base target addresses that respectively target a first memory rank, a second memory rank, a third memory rank and a fourth memory rank, wherein, a first data transfer for the first data burst occurs on a first edge of a first pulse of a data strobe signal for the data bus and a second data transfer for the first data burst occurs on a second edge of the first pulse of the data strobe signal, and wherein, a third data transfer for the second data burst occurs on a first edge of a second pulse of the data strobe signal and a fourth data transfer for the second data burst occurs on a second edge of the second pulse of the data strobe signal, wherein the second pulse immediately follows the first pulse on the data strobe signal.