Memory device, semiconductor system, and data processing system
AssigneeSK hynix Inc.
InventorsYong Sang Park, Joo Young Kim, Min Soo Lim, Min Su Park
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Abstract
A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.
Claims32
A memory device comprising:
- a memory cell array including a plurality of memory regions each identified by a row address and a column address;
- and
- a peripheral circuit configured to access the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap,
- wherein the burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.
A semiconductor system comprising:
- a memory device including:
- a memory cell array including a plurality of memory regions;
- and
- a peripheral circuit configured to access the memory cell array by performing a burst operation supporting a variable burst address gap;
- and
- a memory controller configured to provide the memory device with an address, a burst length and a burst address gap in order to control the burst operation,
- wherein the burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.
A semiconductor system comprising:
- a plurality of memory devices;
- and
- a memory controller coupled to the plurality of memory devices respectively through a plurality of device line groups and coupled to a host device through system lines,
- wherein the memory controller includes a write data processing component configured to:
- receive, from the host device, base device information indicating a base device among the plurality of memory devices,
- map, based on the base device information, the plurality of device line groups and a plurality of system line groups, which are divided from the system lines, and
- transfer data, which are provided from the host device through the plurality of system line groups, to the plurality of device line groups mapped to the plurality of system line groups, respectively.
A data processing system comprising:
- a semiconductor system including:
- a plurality of memory devices;
- and
- a memory controller coupled to the plurality of memory devices respectively through a plurality of device line groups;
- and
- a host device coupled to the memory controller through system lines and configured to provide the memory controller with base device information indicating a base device among the plurality of memory devices,
- wherein the host device is configured to transmit, in order to store a matrix into the semiconductor system, a plurality of elements of the matrix to a plurality of system line groups, which are divided from the system lines, in a parallel way,
- wherein the memory controller is configured to map, based on the base device information, the plurality of system line groups to the plurality of device line groups to store the matrix into the plurality of memory devices, and
- wherein a precision degree of the matrix is the same as a bit width of each of the plurality of device line groups.
Dependencies are inferred from the claim text.