Back to results
US 11,699,465 B2Granted
Memory device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsTatsuya Onuki, Shuhei Nagatsuka
Life of this patent
Estimating the term…
Abstract
A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.
Claims13
A semiconductor device comprising:
- a first layer comprising a circuit;
- and
- a second layer over the first layer, the second layer comprising:
- a first memory cell comprising a first transistor comprising an oxide semiconductor in a channel formation region;
- and
- a second memory cell comprising a second transistor comprising an oxide semiconductor in a channel formation region,
- wherein each of the first transistor and the second transistor comprises a front gate and a back gate,
- wherein the back gate of the first transistor is electrically connected to the back gate of the second transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to a first electrode of a first capacitor,
- wherein one of a source and a drain of the second transistor is electrically connected to a first electrode of a second capacitor,
- wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,
- wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
- wherein the circuit comprises a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,
- wherein a gate of the third transistor is electrically connected to the first wiring,
- wherein a gate of the fifth transistor is electrically connected to the second wiring,
- wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
- wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor, and
- wherein a gate of the fourth transistor is electrically connected to a gate of the sixth transistor.
15 more elements
A semiconductor device comprising:
- a first layer comprising a circuit;
- and
- a second layer over the first layer, the second layer comprising:
- a first memory cell comprising a first transistor;
- and
- a second memory cell comprising a second transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to a first electrode of a first capacitor,
- wherein one of a source and a drain of the second transistor is electrically connected to a first electrode of a second capacitor,
- wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,
- wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
- wherein the circuit comprises a third transistor and a fourth transistor,
- wherein a gate of the third transistor is electrically connected to the first wiring, and
- wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor.
10 more elements
A semiconductor device comprising:
- a first layer comprising a circuit;
- and
- a second layer over the first layer, the second layer comprising:
- a first memory cell comprising a first transistor;
- and
- a second memory cell comprising a second transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to a first electrode of a first capacitor,
- wherein one of a source and a drain of the second transistor is electrically connected to a first electrode of a second capacitor,
- wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,
- wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
- wherein the circuit comprises a third transistor and a fourth transistor,
- wherein a gate of the third transistor is electrically connected to the first wiring,
- wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, and
- wherein a first material of a channel formation region of each of the first transistor and the second transistor is different from a second material of a channel formation region of each of the third transistor and the fourth transistor.
11 more elements
Dependencies are inferred from the claim text.