US 11,699,408 B2 · Performing asynchronous memory clock changes on multi-display systems

Abstract

Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.

Claims20

Dependent claims

An apparatus comprising:

a tracking circuitry, wherein responsive to determining that a condition for changing a memory clock frequency of a memory subsystem is satisfied, the tracking circuitry is configured to:
track vertical blanking interval (VBI) timing for a first display device to detect an occurrence of a VBI of the first display device;
and
cause a second display device, different from the first display device, to transition into panel self-refresh (PSR) mode;
and
a frequency adjustment circuitry configured to cause an adjustment to be made to the memory clock frequency when the VBI of the first display device is detected to occur at a same time that the second display device is in the PSR mode.

3 more elements

Dependencies are inferred from the claim text.

Performing asynchronous memory clock changes on multi-display systems

Life of this patent

Performing asynchronous memory clock changes on multi-display systems

Life of this patent

Abstract

Claims20