US 11,699,397 B2 · Display substrate, manufacturing method thereof, and display device having the same

Abstract

The present disclosure provides a display substrate, a manufacturing method and a display device. The display substrate comprises a scan driving circuit and a display area, wherein the scan driving circuit comprises a plurality of shift register units, a first voltage signal line, a second voltage signal line, a first clock signal line, and a second clock signal line, all of which extend in a first direction; and the display area comprises at least one driving transistor configured to drive a light-emitting element for display. At least one of the plurality of shift register units comprises an output circuit and a signal output line, wherein the output circuit is coupled to the first voltage signal line, the second voltage signal line, and the signal output line, and the signal output line extends in a second direction intersecting the first direction. The output circuit comprises a transistor that is provided between the first voltage signal line and the second voltage signal line.

Drawings

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Drawings

Claims20

Dependent claims

A display substrate, comprising a scan driving circuit and a display area provided on a base substrate, the scan driving circuit comprising a plurality of shift register units and further comprising a first voltage signal line, a second voltage signal line, a first clock signal line, and a second clock signal line, all of which extend in a first direction, and the display area comprising at least one driving transistor configured to drive a light-emitting element for display;

wherein at least one of the plurality of shift register units comprises an output circuit and a signal output line, wherein the output circuit is coupled to the first voltage signal line, the second voltage signal line, and the signal output line, and the signal output line extends in a second direction intersecting the first direction;
wherein an orthogonal projection of one or more transistors included in the output circuit on the base substrate is provided between an orthogonal projection of the first voltage signal line on the base substrate and an orthogonal projection of the second voltage signal line on the base substrate;
wherein the at least one of the plurality of shift register units further comprises an output capacitor, a first transistor, a first node control transistor, a second node control transistor, and a third node control transistor;
wherein a second electrode of the first transistor is coupled to one of a first plate and a second plate of the output capacitor, a first electrode of the first transistor is coupled to the first voltage signal line that is configured to provide a high-level signal, and a gate electrode of the first transistor is coupled to one of a first electrode and a second electrode of the third node control transistor;
wherein the output circuit comprises an output transistor and an output reset transistor, which are arranged along the first direction;
a first electrode of the output reset transistor is coupled to the first voltage signal line, and a first electrode of the output transistor is coupled to the second voltage signal line;
a second electrode of the output transistor and a second electrode of the output reset transistor are both coupled to the signal output line;
wherein active layers of the output transistor and the output reset transistor are formed by one continuous first semiconductor layer;
and
the first semiconductor layer and the signal output line are arranged along the first direction,
wherein a gate electrode of the output reset transistor comprises at least one output reset gate pattern, the first electrode of the output reset transistor comprises at least one first electrode pattern, and the second electrode of the output reset transistor comprises at least one second electrode pattern;
the output reset gate pattern is located between the first electrode pattern and the second electrode pattern, which are adjacent to each other;
and
the second electrode pattern, the output reset gate pattern, and the first electrode pattern all extend in the second direction intersecting the first direction, or
wherein a gate electrode of the output transistor comprises at least one output gate pattern, the first electrode of the output transistor comprises at least one third electrode pattern, and the second electrode of the output transistor comprises at least one fourth electrode pattern;
the output gate pattern is located between the third electrode pattern and the fourth electrode pattern, which are adjacent to each other;
the fourth electrode pattern, the output gate pattern, and the third electrode pattern all extend in the second direction intersecting the first direction;
and
the second electrode pattern in the output reset transistor that is closest to the gate electrode of the output transistor is multiplexed as the fourth electrode pattern of the output transistor.

16 more elements

wherein at least one of the plurality of shift register units comprises an output circuit and a signal output line, wherein the output circuit is coupled to the first voltage signal line, the second voltage signal line, and the signal output line, and the signal output line extends in a second direction intersecting the first direction;
wherein an orthogonal projection of one or more transistors included in the output circuit on the base substrate is provided between an orthogonal projection of the first voltage signal line on the base substrate and an orthogonal projection of the second voltage signal line on the base substrate;
wherein the at least one of the plurality of shift register units further comprises an output capacitor, a first transistor, a first node control transistor, a second node control transistor, and a third node control transistor;
wherein a second electrode of the first transistor is coupled to one of a first plate and a second plate of the output capacitor, a first electrode of the first transistor is coupled to the first voltage signal line that is configured to provide a high-level signal, and a gate electrode of the first transistor is coupled to one of a first electrode and a second electrode of the third node control transistor;
wherein the output circuit comprises an output transistor and an output reset transistor, which are arranged along the first direction;
a first electrode of the output reset transistor is coupled to the first voltage signal line, and a first electrode of the output transistor is coupled to the second voltage signal line;
a second electrode of the output transistor and a second electrode of the output reset transistor are both coupled to the signal output line;
wherein the scan driving circuit further comprises a third voltage signal line, and the at least one shift register unit further comprises a first capacitor, a second capacitor, a second transistor, a first capacitor connecting transistor, a second capacitor connecting transistor, and an input transistor
a first electrode of the second transistor is coupled to a first plate of the first capacitor, a second electrode of the second transistor is coupled to a second electrode of the first capacitor connecting transistor, and a gate electrode of the second transistor is coupled to a gate electrode of the third node control transistor;
a gate electrode of the first capacitor connecting transistor and a gate electrode of the second capacitor connecting transistor are coupled to a second plate of the first capacitor, the second electrode of the first capacitor connecting transistor is coupled to the first plate of the first capacitor, and a first electrode of the first capacitor connecting transistor is coupled to the gate electrode of the second transistor;
a first electrode of the second capacitor connecting transistor is coupled to the first voltage signal line, the gate electrode of the second capacitor connecting transistor is coupled to a second electrode of the second node control transistor, and a second electrode of the second capacitor connecting transistor is coupled to the other one of the first electrode and the second electrode of the third node control transistor;
a first electrode of the first node control transistor is coupled to a gate electrode of the second node control transistor, and a gate electrode of the first node control transistor is coupled to a second plate of the second capacitor;
a second electrode of the second node control transistor is coupled to a second electrode of the first node control transistor, the gate electrode of the second node control transistor is coupled to the second clock signal line, and a first electrode of the second node control transistor is coupled to the third voltage signal line;
a gate electrode of the input transistor is coupled to a gate electrode of the second node control transistor, a first electrode of the input transistor is coupled to an input signal terminal, and a second electrode of the input transistor is coupled to the second plate of the second capacitor;
the gate electrode of the third node control transistor is coupled to the first clock signal line;
the other one of the first plate and the second plate of the output capacitor is coupled to the first voltage signal line, and the second plate of the output capacitor is coupled to a gate electrode of the output reset transistor;
the second plate of the second capacitor is coupled to a gate electrode of the output transistor, and a first plate of the second capacitor is coupled to the first clock signal line;
a second electrode of the output transistor and a second electrode of the output reset transistor are both coupled to the signal output line.

15 more elements

Dependencies are inferred from the claim text.

Description31,463 words

Summary4,942 words

#The present application is the U.S. national phase of PCT Application No. PCT/CN2020/079482 filed on Mar. 16, 2020, which is incorporated herein by reference in its entity.

#The present disclosure relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display device having the same.

#Active Matrix Organic Light-Emitting Diode (hereinafter abbreviated to AMOLED) display panels are widely used in various fields due to their low power consumption, low production cost, and wide color gamut.

Brief description of the drawings15 figures

#FIG. 1 is a circuit diagram of at least one embodiment of at least one shift register unit included in a display substrate according to an embodiment of the present disclosure;

#FIG. 2A is an operation timing diagram of at least one embodiment of the shift register unit shown in FIG. 1;

#FIG. 2B is a schematic diagram of an area division of the display substrate according to at least one embodiment of the present disclosure;

Detailed description26,039 words

#The technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part, rather than all, of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without exercising any inventive work shall fall within the protection scope of the present disclosure.

#As shown in FIG. 1, the present disclosure provides a display substrate, which includes a scan driving circuit located in an edge area of a display substrate. The scan driving circuit includes a first voltage signal line VGH, a second voltage signal line VGL1, a third voltage signal line VGL2, a first clock signal line CB, a second clock signal line CK and a signal output line EOUT. The scan driving circuit further includes a plurality of shift register units.

#As shown in FIG. 1, at least one embodiment of at least one of the plurality of shift register units includes an output reset transistor T9, an output transistor T10, an output capacitor C3, a first capacitor C1, a second capacitor C2, a first transistor T8, a second transistor T7, a first capacitor connecting transistor T6, a second capacitor connecting transistor T5, a first node control transistor T2, a second node control transistor T3, an input transistor T1, and a third node control transistor T4.

Display substrate, manufacturing method thereof, and display device having the same

Life of this patent

Display substrate, manufacturing method thereof, and display device having the same

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims20

Description31,463 words

Drawings

Classification11 codes

Life of this patent

Description31,463 words