Pixel circuit, driving method thereof and display device

A pixel circuit, comprising:

• a reset sub-circuit, a drive sub-circuit, a write sub-circuit, a compensation sub-circuit, a light-emitting control sub-circuit and a light-emitting element,
• wherein the drive sub-circuit comprises a drive transistor;
• a first electrode of the drive transistor is connected with the write sub-circuit;
• the reset sub-circuit is configured to be connected with an initial voltage terminal, a third voltage terminal and the drive sub-circuit and is configured to write an initial voltage of the initial voltage terminal into a gate electrode of the drive transistor in the drive sub-circuit and write a voltage of the third voltage terminal into a first electrode or a second electrode of the drive transistor;
• the drive transistor is in the on-bias state in the reset period;
• the write sub-circuit is configured to be connected with a data voltage terminal and the drive sub-circuit and is configured to write a data voltage of the data voltage terminal into the drive sub-circuit;
• the compensation sub-circuit is connected with the drive sub-circuit and is configured to compensate a threshold voltage of the drive transistor in the drive sub-circuit;
• the light-emitting control sub-circuit is configured to be connected with a luminescent control signal terminal, a first voltage terminal, the drive sub-circuit and an anode of the light-emitting element;
• a cathode of the light-emitting element is connected with a second voltage terminal;
• the light-emitting control sub-circuit is configured to transmit a drive current, generated by the drive sub-circuit under action of the first voltage terminal, the second voltage terminal and the data voltage written into the drive sub-circuit, to the light-emitting element;
• and
• the light-emitting element is configured to emit light according to the drive current,
• wherein the reset sub-circuit comprises a gate electrode reset sub-sub-circuit and a first electrode reset sub-sub-circuit;
• the gate electrode reset sub-sub-circuit is configured to be connected with the initial voltage terminal and the gate electrode of the drive transistor and is configured to write the initial voltage of the initial voltage terminal into the gate electrode of the drive transistor;
• the first electrode reset sub-sub-circuit is configured to be connected with the third voltage terminal and the first electrode of the drive transistor and is configured to write the voltage of the third voltage terminal into the first electrode of the drive transistor;
• or
• the reset sub-circuit comprises a gate electrode reset sub-sub-circuit and a second electrode reset sub-sub-circuit;
• the gate electrode reset sub-sub-circuit is configured to be connected with the third voltage terminal and the second electrode of the drive transistor;
• and the second electrode reset sub-sub-circuit is configured to write the voltage of the third voltage terminal into the second electrode of the drive transistor,
• wherein the gate electrode reset sub-sub-circuit comprises a fifth transistor;
• a gate electrode of the fifth transistor is configured to be connected with a fifth gate signal terminal;
• a first electrode of the fifth transistor is connected with the gate electrode of the drive transistor;
• and a second electrode of the fifth transistor is configured to be connected with the initial voltage terminal,
• wherein in a case where the reset sub-circuit is further connected with the anode of the light-emitting element, the gate electrode reset sub-sub-circuit comprises a sixth transistor;
• a gate electrode of the sixth transistor is configured to be connected with a sixth gate signal terminal;
• a first electrode of the sixth transistor is connected with the anode of the light-emitting element,
• wherein the third voltage terminal is configured to be connected with a reference voltage terminal;
• in a case where the reset sub-circuit comprises the first electrode reset sub-sub-circuit, the first electrode reset sub-sub-circuit comprises a seventh transistor;
• a gate electrode of the seventh transistor is configured to be connected with a seventh control signal terminal;
• a first electrode of the seventh transistor is configured to be connected with the reference voltage terminal;
• and a second electrode of the seventh transistor is connected with the first electrode of the drive transistor;
• the fifth gate signal terminal and the sixth gate signal terminal receive different signals,
• the compensation sub-circuit comprises a second transistor;
• a gate electrode of the second transistor is configured to be connected with a second gate signal terminal;
• a first electrode of the second transistor is connected with the gate electrode of the drive transistor;
• a second electrode of the second transistor is connected with the second electrode of the drive transistor;
• and
• the second transistor is an N-type transistor.