Semiconductor device and display driver IC using the same

A semiconductor device, comprising:

• a semiconductor substrate including an active region, the active region defined in a well impurity layer having a first conductivity type;
• a gate electrode on the active region;
• and
• a gate insulating layer between the gate electrode and the active region,
• wherein the active region comprises
• a source region at a first side of the gate electrode and a drain region at a second side of the gate electrode, the source region and the drain region having a second conductivity type,
• a channel region between the source and drain regions, the channel region having the first conductivity type,
• a first halo region in contact with the source region and a second halo region in contact with the drain region, the first halo region and the second halo region having the first conductivity type, and
• a slit well region between the first and second halo regions, the slit well region having the first conductivity type,
• wherein a top surface of the channel region comprises a first point in contact with the source region, a second point in contact with the drain region, a third point at a center point of the top surface, a fourth point between the first and third points, and a fifth point between the third and second points,
• wherein the first and second points have a first dopant concentration,
• wherein the third point has a second dopant concentration,
• wherein the fourth and fifth points have a third dopant concentration,
• wherein the third dopant concentration is lower than the first dopant concentration, and
• wherein the third dopant concentration is lower than the second dopant concentration.

A display driver integrated circuit (IC), comprising:

• a source driver including an amplifier circuit;
• and
• a gate driver, wherein the source driver and the gate driver are configured to drive a pixel of a display panel,
• wherein a metal-oxide-semiconductor (MOS) transistor of the amplifier circuit comprises
• a semiconductor substrate including a well impurity layer having a first conductivity type,
• a source region and a drain region in an upper portion of the well impurity layer, the source region and the drain region spaced apart from each other in a first direction, and the source region and the drain region having a second conductivity type,
• a channel region between the source and drain regions, the channel region having the first conductivity type,
• a slit well region at a center point of the channel region, the slit well region having the first conductivity type, and
• a gate electrode on the channel region,
• wherein the gate electrode has a first length in the first direction,
• wherein a top surface of the slit well region has a second length in the first direction, and
• wherein a ratio of the second length to the first length is in a range from 0.2 to 0.6.