Display panel and display device with reduced charge accumulation in semiconductor layer

A display panel, having a display region and a frame region outside the display region, the display panel comprising:

• a base substrate;
• a buffer layer on a side of the base substrate, wherein the buffer layer includes an a-Si layer;
• a semiconductor layer on a side of the buffer layer away from the base substrate;
• an insulation layer on a side of the semiconductor layer away from the base substrate;
• and
• a power signal layer on a side of the insulation layer away from the base substrate, wherein the power signal layer includes a plurality of first power voltage lines in the display region;
• and the power signal layer is electrically connected to a power signal terminal which alternately outputs a positive voltage signal and a negative voltage signal,
• wherein the outputted positive voltage signal drives charges of the buffer layer to accumulate towards the semiconductor layer and the outputted negative voltage signal dissipates the charges accumulated in the semiconductor layer, and a time length of a single output of the negative voltage signal from the power signal terminal is less than or equal to 1 ms and greater than zero.