Circuit arrangements having reduced dependency on layout environment

A method comprising:

• fabricating an active-region semiconductor structure on an insulator support;
• fabricating gate-conductors intersecting the active-region semiconductor structure;
• fabricating terminal-conductors intersecting the active-region semiconductor structure;
• dividing the active-region semiconductor structure into multiple active-region semiconductor structures that include a middle active-region structure between a group-one active-region structure and a group-two active-region structure, whereby forming a first boundary gate-conductor at a first end of the middle active-region structure, a second boundary gate-conductor at a second end of the middle active-region structure, a group-one boundary gate-conductor at a first end of the group-one active-region structure, and a group-two boundary gate-conductor at a first end of the group-two active-region structure;
• depositing an inter-layer dielectric material covering the middle active-region structure, the group-one active-region structure, the group-two active-region structure, and the gate-conductors;
• forming a first trench after removing a first gate-conductor to divide the group-one active-region structure into a first part and a second part and forming a second trench after removing a second gate-conductor to divide the group-two active-region structure into a first part and a second part;
• and
• forming a group-one isolation structure in the first trench and forming a group-two isolation structure in the second trench.

An integrated circuit comprising:

• a middle first-type active-region structure between a group-one first-type active-region structure and a group-two first-type active-region structure, wherein the middle first-type active-region structure is aligned with the group-one first-type active-region structure and the group-two first-type active-region structure along a first direction;
• a main circuit comprising,
• a first boundary gate-conductor intersecting the middle first-type active-region structure at a first end of the middle first-type active-region structure, and
• adjacent gate-conductors separated by a pitch distance equal to a contacted poly pitch (“CPP”);
• a group-one circuit comprising,
• a group-one boundary gate-conductor intersecting the group-one first-type active-region structure at a first end of the group-one first-type active-region structure and is separated from the first boundary gate-conductor in the main circuit by a pitch distance of one CPP, and
• a group-one isolation structure separating the group-one first-type active-region structure into a first part in the group-one circuit and a second part in a first adjacent circuit, and wherein a width of the group-one isolation structure along the first direction is less than one half of the CPP;
• and
• a group-two circuit comprising,
• a group-two isolation structure separating the group-two first-type active-region structure into a first part in the group-two circuit and a second part in a second adjacent circuit, and wherein a width of the group-two isolation structure along the first direction is less than one half of the CPP.