US 11,699,010 B2 · Method and system for reducing migration errors

Abstract

A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

Claims20

Dependent claims

A method of manufacturing a semiconductor device, the method comprising:

reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, at least the second netlist being stored on a non-transitory computer-readable medium, the reducing errors including:
inspecting a timing constraint list corresponding to the second netlist for addition candidates;
generating a first version of the second netlist having a first number of comparison points which are to be used in a logic equivalence check process (LEC), the first number of comparison points being based on the addition candidates;
performing the LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors;
and
revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

3 more elements

A system for reducing errors in a migration from a first netlist to a second netlist, the first and second netlists representing a same circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium, the system comprising:

at least one processor;
and
at least one memory including computer program code for one or more programs;
wherein the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute:
inspecting a timing constraint list corresponding to the second netlist for addition candidates;
generating a first version of the second netlist having a first number of comparison points which are to be used in a logic equivalence check process (LEC), the first number of comparison points being based on the addition candidates;
performing the LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors;
and
revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

6 more elements

A method of migrating from a first netlist to a second netlist, the first and second netlists representing a same circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium, the migrating including:

inspecting a timing constraint list corresponding to the second netlist to identify combinational circuits as addition candidates;
converting selected glass boxes of the identified combinational circuits into supplemental black boxes to generate a first version of the second netlist having a first number of comparison points which are to be used in a logic equivalence check process (LEC), the first number of comparison points being based on the addition candidates;
performing the LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors;
and
revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

2 more elements

Dependencies are inferred from the claim text.

Method and system for reducing migration errors

Life of this patent

Method and system for reducing migration errors

Life of this patent

Abstract

Claims20