Integrated circuit design method and system
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorTien-Chien Huang
Life of this patent
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Abstract
A method of generating a layout diagram of an IC device includes assigning a leakage constraint to a first schematic net of the IC device and determining a violation of the leakage constraint based on a dummy gate region. The IC layout diagram includes the dummy gate region between a first component of the first schematic net and a second component of a second schematic net of the IC device. The method includes modifying the IC layout diagram in response to the leakage constraint violation, and generating a layout file based on the modified IC layout diagrams.
Claims20
An integrated circuit (IC) layout diagram generation system comprising:
- a processor;
- and
- a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the processor to generate a layout diagram of an IC device by:
- adding a circuit element at a drain terminal of a transistor in a first schematic net of a netlist of an IC device, wherein the circuit element is configured to emulate a leakage path corresponding to a dummy gate region adjacent to the transistor;
- determining that a circuit performance parameter is affected by the added circuit element;
- in response to the determination, modifying the first schematic net of the netlist to include a net attribute comprising a maximum leakage current value;
- and
- storing the netlist including the modified first schematic net in the non-transitory, computer readable storage medium or another non-transitory, computer readable storage medium.
An integrated circuit (IC) layout diagram generation system comprising:
- a processor;
- and
- a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the processor to generate a layout diagram of an IC device by:
- adding a circuit element at a drain terminal of a first transistor in a first schematic net of a netlist of an IC device, the circuit element comprising one of a current source, a resistor, or a second transistor configured to emulate a leakage path corresponding to a dummy gate region adjacent to the first transistor;
- determining that a circuit performance parameter is affected by the added circuit element;
- in response to the determination, modifying the first schematic net of the netlist to include a net attribute comprising a maximum leakage current value;
- and
- storing the netlist including the modified first schematic net in the non-transitory, computer readable storage medium or another non-transitory, computer readable storage medium.
A method of generating an integrated circuit (IC) layout diagram, the method comprising:
- adding a circuit element at a drain terminal of a first transistor in a first schematic net of a netlist of an IC device, wherein the circuit element is configured to emulate a leakage path corresponding to a dummy gate region adjacent to the first transistor;
- determining that a circuit performance parameter is affected by the added circuit element;
- in response to the determination, modifying the first schematic net of the netlist to include a net attribute comprising a maximum leakage current value;
- and
- storing the netlist including the modified first schematic net in a non-transitory, computer readable storage medium.
Dependencies are inferred from the claim text.