Peripheral access on a secure-aware bus system

A method of operating an integrated-circuit device, wherein the integrated-circuit device comprises:

• a processor;
• a peripheral component;
• and
• a bus system, connected to the processor and to the peripheral component, and configured to carry secure bus transactions and non-secure bus transactions,
• wherein the bus system is configured to carry security-state signals for distinguishing between the secure bus transactions and the non-secure bus transactions;
• wherein the peripheral component comprises a register interface, accessible over the bus system, the register interface comprising a hardware register,
• the method comprising the peripheral component being in a secure-in-and-non-secure-out state and, while the peripheral component is in the secure-in-and-non-secure-out state:
• preventing, by a hardware filter logic based at least on the security-state signals, the non-secure bus transactions from accessing the hardware register of the peripheral component, but allowing, by the hardware filter logic based at least on the security-state signals, the secure bus transactions to access the peripheral component;
• allowing, by the peripheral component, an incoming secure bus transaction to access the hardware register;
• and
• initiating, by the peripheral component, only non-secure bus transactions on the bus system.

An integrated-circuit device comprising:

• a processor;
• a peripheral component, wherein the peripheral component is a DAC (Digital-to-Analog Converter) peripheral, or a PWM (Pulse Width Modulation) peripheral, or a quadrature decoder peripheral, or a cryptographic co-processor, or a GPIO (General-Purpose Input-Output) control peripheral;
• and
• a bus system, connected to the processor and to the peripheral component, and configured to carry bus transactions,
• wherein:
• the peripheral component comprises a register interface, accessible over the bus system, the register interface comprising a first hardware register and a second hardware register;
• the bus system is configured to carry security-state signals for distinguishing between secure bus transactions and non-secure bus transactions;
• the peripheral component comprises an input for receiving the security-state signals from the bus system;
• and
• the peripheral component supports a split-security state in which the peripheral component, based at least on the security-state signals, is configured to:
• prevent a non-secure bus transaction from accessing the first hardware register;
• allow a secure bus transaction to access the first hardware register;
• and
• allow a non-secure bus transaction to access the second hardware register.

A method of operating an integrated-circuit device, wherein the integrated-circuit device comprises:

• a processor;
• a peripheral component, wherein the peripheral component is a DAC (Digital-to-Analog Converter) peripheral, or a PWM (Pulse Width Modulation) peripheral, or a quadrature decoder peripheral, or a cryptographic co-processor, or a GPIO (General-Purpose Input-Output) control peripheral;
• and
• a bus system, connected to the processor and to the peripheral component, and configured to carry secure bus transactions and non-secure bus transactions,
• wherein the peripheral component comprises a register interface, accessible over the bus system, the register interface comprising a first hardware register and a second hardware register,
• wherein the bus system is configured to carry security-state signals for distinguishing between the secure bus transactions and the non-secure bus transactions;
• the peripheral component comprises an input for receiving the security-state signals from the bus system;
• the method comprising:
• receiving, by the peripheral component, the secure bus transactions and the non-secure bus transactions from the bus system;
• and
• while the peripheral component is in a split-security state, based at least on the security-state signals:
• preventing, by the peripheral component, a non-secure bus transaction from accessing the first hardware register;
• allowing, by the peripheral component, a secure bus transaction to access the first hardware register;
• and
• allowing, by the peripheral component, a non-secure bus transaction to access the second hardware register.