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US 11,698,873 B2Granted
Interleaving in multi-level data cache on memory bus
AssigneenCorium
InventorArvindhkumar Lalam
Life of this patent
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Abstract
This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The memory-storage combine is adapted to allow access, through the memory bus, a combination of random access memory (RAM) based data storage and non-volatile mass data storage. A controller is arranged to address the both RAM based data storage and the non-volatile mass data storage as part of a unified address space in the manner of RAM.
Claims13
A computing system comprising:
- a processor interconnected to a memory bus;
- a memory-storage combine, interconnected to the memory bus,
- wherein each of the memory-storage combine, of a plurality of memory-storage combines, comprises of an NVDIMM,
- wherein the processor is directly connected to a plurality of NVDIMMs,
- wherein the memory-storage combine also comprises a first and a second type of memory devices connected to respective levels of controllers of a non-volatile dual-inline memory module (NVD) controller, within the memory-storage combine,
- wherein the first and the second type of memory devices are connected to a mass storage via respective protocols of the NVD controller,
- wherein an IO connection of the processor is accessing the memory-storage combine via a different path from the memory bus,
- wherein a controller is arranged to address the combination of different memory types as part of a unified address space via the memory bus.
5 more elements
A computing system comprising:
- a processor interconnected to a memory bus;
- a memory-storage combine, interconnected to the memory bus
- wherein each of the memory-storage combine, of a plurality of memory-storage combines, comprises of an NVDIMM,
- wherein the processor is directly connected to a plurality of NVDIMMs,
- wherein the plurality of NVDIMMs are connected to a mass storage, within the memory-storage combine,
- wherein the mass storage provides a final resting place for data passing between the processor, the plurality of NVDIMMs and the mass storage,
- wherein an interleaver, within the processor, manipulates packets of a data available in an original pattern so that the data is distributed among the plurality of NVDIMMs in an organized pattern,
- wherein a de-interleaver, within the processor, reorganizes packets of the data retrieved from the plurality of NVDIMMs and restores the data to the original pattern,
- wherein an IO connection of the processor accesses the memory-storage combine via a different path from the memory bus, and
- wherein a controller is arranged to address the combination of different memory types as part of a unified address space via the memory bus.
7 more elements
Dependencies are inferred from the claim text.