US 11,698,869 B1Granted

Computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) engines

AssigneeNVIDIA Corporation

InventorsVaishali Kulkarni, Naveen Cherukuri, Raymond Wong, Adam Hendrickson, Gobikrishna Dhanuskodi, Wish Gandhi

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Abstract

The subject application relates to computing an authentication tag for partial transfers scheduled across multiple direct memory access (DMA) engines. Apparatuses, systems, and techniques are described for computing an authentication tag for a data transfer when the data transfer is scheduled as partial transfers across a specified number of direct memory access (DMA) engines. An orchestration circuit stores partial authentication tags, computed by the DMA engines, and corresponding adjustment exponents during one or more rounds in which the partial transfers are scheduled and processed by the specified number of DMA engines. During a last round, a combined authentication tag can be computed based on the partial authentication tags and the corresponding adjustment exponents stored by the orchestration circuit during the rounds.

Claims20

Dependent claims

An accelerator circuit comprising:

a secure memory;
a scheduler circuit to receive a first data transfer of a first size and split the first data transfer into a set of partial transfers;
and
a direct memory access (DMA) circuit comprising a logical DMA engine, an orchestration circuit, and a plurality of DMA engines, each DMA engine of the plurality of DMA engines comprising a cryptographic circuit that implements an authenticated encryption algorithm to encrypt retrieved data from the secure memory or decrypt received data to be stored in the secure memory, wherein:
the logical DMA engine is to schedule a first partial transfer to a first DMA engine of the plurality of DMA engines and store a first adjustment exponent in a first buffer in the orchestration circuit, the first buffer associated with the first DMA engine;
the first DMA engine is to calculate a first partial authentication tag for the first partial transfer and store the first partial authentication tag in the first buffer;
the logical DMA engine is to schedule a second partial transfer to a second DMA engine of the plurality of DMA engines and store a second adjustment exponent in a second buffer in the orchestration circuit, the second buffer associated with the second DMA engine;
the second DMA engine is to calculate a second partial authentication tag for the second partial transfer and store the second partial authentication tag in the second buffer;
and
the orchestration circuit is to calculate a first combined authentication tag for the first data transfer based on at least the first adjustment exponent, the first partial authentication tag, the second adjustment exponent, and the second partial authentication tag.

7 more elements

A method of operating an accelerator circuit, the method comprising:

receiving a first data transfer of a first size;
splitting the first data transfer into a first set of data transfer portions, each data transfer portion being less than the first size;
during a first round,
scheduling a subset of the first set of data transfer portions to a plurality of direct memory access (DMA) engines, each comprising a cryptographic hardware engine,
storing a first subset of partial authentication tags, computed by the plurality of DMA engines, and a first subset of corresponding adjustment exponents, and
determining a partial authentication tag for the first round based on the first subset of partial authentication tags and corresponding adjustment exponents;
and
during a last round, determining an authentication tag for the first data transfer by combining the partial authentication tag from each round to obtain a combined authentication tag and combining a length of the first data transfer with the combined authentication tag.

5 more elements

An accelerator circuit comprising:

a copy engine (CE) comprising a plurality of Advanced Encryption Standard Galois Counter Mode (AES-GCM) hardware engines each configured to perform encryption and authentication, wherein the CE comprises secure memory to store a context comprising an encryption key, an initialization vector (IV), and a block counter;
and
an engine scheduler coupled to the CE, wherein:
the engine scheduler is to:
receive an encryption or decryption operation descriptor of a data transfer of a specified size for an application;
and
split the data transfer into a set of partial transfers, each partial transfer having a fixed size less than the specified size;
the copy engine (CE), during a first round, is to:
schedule a subset of the set of partial transfers to the plurality of AES-GCM hardware engines;
store a first subset of partial authentication tags, computed by the plurality of AES-GCM hardware engines, and a first subset of corresponding adjustment exponents, and
determine a partial authentication tag for the first round based on the first subset of partial authentication tags and the first subset of corresponding adjustment components;
and
the copy engine (CE), during a last round, is to:
determine an authentication tag for the data transfer by combining the partial authentication tag from each round to obtain a combined authentication tag, combining a length of the data transfer with the combined authentication tag, and encrypting the combined authentication tag with the IV.

11 more elements

Dependencies are inferred from the claim text.