Method, system, and apparatus for supporting multiple address spaces to facilitate data movement

A method for supporting multiple memory address spaces to facilitate data movement, the method comprising:

• receiving, at a first input/output memory management unit (IOMMU), context data of a second IOMMU, wherein each of the first and second IOMMUs includes a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to respective IOMMUs;
• synchronizing, by the first IOMMU, the plurality of MMIO registers of the first IOMMU with the plurality of MMIO registers of at least the second IOMMU;
• receiving, from a peripheral component endpoint coupled to the first IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the second IOMMU;
• accessing, by the first IOMMU, the plurality of MMIO registers of the first IOMMU based on context data of the DMA request;
• accessing, from the first IOMMU, page tables referenced by a context belonging to the second IOMMU based on the accessed plurality of MMIO registers;
• performing, by the first IOMMU, address translation on the DMA request using the accessed page tables;
• and
• performing, by the first IOMMU, a memory access based on the DMA request and the translated address.

An input/output memory management unit (IOMMU) comprising:

• a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU;
• and
• hardware control logic operative to:
• synchronize the plurality of MMIO registers of the at least the second IOMMU;
• receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU;
• access the plurality of MMIO registers of the IOMMU based on context data of the DMA request;
• and
• access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.

A data processing system, comprising:

• a host processor;
• a memory;
• a data fabric coupled to the host processor and to the memory;
• a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric;
• and
• a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding IOMMU of the first and second IOMMUs,
• wherein each of the first and second IOMMUs comprises hardware control logic operative to:
• synchronize the first and second IOMMUs;
• receive, from the peripheral component endpoint coupled to the first IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the second IOMMU;
• and
• the first IOMMU configured to provide direct memory access to the memory address space belonging to the second IOMMU in response to the DMA request.