Efficient and selective sparing of bits in memory systems
AssigneeInternational Business Machines Corporation
InventorsStephen Glancy, Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain
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Abstract
A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.
Claims19
A non-transitory computer readable medium comprising instructions that when executed configure a memory system to:
- detect a first error in a first memory bit location in at least one memory storage device;
- remap and store data to be stored at the first memory bit location where the first error was detected to a spare bit lane;
- and
- store location information in the spare bit lane that identifies at least one of:
- a location of the first error, an error correction code (ECC), or a combination thereof.
A method for storing electronic data, the method comprising:
- reading spare bit lane data in a spare bit lane in a memory storage device configured to store the electronic data, wherein the memory storage device has a plurality of spare bits configured in the spare bit lane for remapping one or more bit errors detected during an operation;
- and
- reading a location address in the spare bit lane to identify where to use the spare bit lane data read from the spare bit lane.
A non-transitory computer readable medium comprising instructions that when executed configure a memory system to:
- read spare bit lane data in a spare bit lane in a memory storage device configured to store data, wherein the memory storage device has a plurality of spare bits configured in the spare bit lane for remapping a bit error detected during an operation;
- and
- read a location address in the spare bit lane to identify where to use the spare bit lane data read from the spare bit lane.
Dependencies are inferred from the claim text.