Semiconductor memory

A semiconductor memory, comprising:

• three storage arrays;
• two verification modules, wherein each of the two verification modules corresponds to storage arrays of the three storage arrays, the each verification module is configured to verify whether an error occurs in data information of the corresponding storage arrays, and the each verification module is connected to a group of global data buses;
• and
• a plurality of gating circuits, wherein the gating circuits are connected between the three storage arrays and the global data buses, and the gating circuits are configured to control an activation of a data transmission path between the global data buses and the three storage arrays,
• wherein the three storage arrays comprise a first array, a second array and a third array;
• the second array is connected to two second gating circuits, and each of the two second gating circuits is connected with a corresponding one of the global data buses,
• wherein the first array is connected to at least one first gating circuit, and the third array is connected to at least one third gating circuit,
• wherein the first gating circuit, the second gating circuit and the third gating circuit, which are connected to a same global data bus, are turned on time-divisionally.