Memory, memory controlling method and system

A memory controlling method, the memory includes a memory cell array, an instruction decoder, a controller and a chip selection pin, the method comprising:

• in response to the chip select pin receiving a chip select signal, the memory entering a power-down state from a deep power-down state;
• in response to the instruction decoder receiving a power-down state instruction, the memory entering the power-down state from a standby state;
• in response to the instruction decoder receiving a deep power-down state instruction, the memory entering the deep power-down state from the standby state or power-down state,
• wherein, in the standby state, the instruction decoder, the memory cell array, the input and output interface and the controller are enabled;
• in the power-down state, the instruction decoder is enabled;
• and in the deep power-down state, the instruction decoder and controller are disabled.

A system comprising:

• a host;
• an interface bus;
• a memory coupled to the host by connecting a input and output interface to the interface bus, wherein the memory comprises:
• a memory cell array;
• an instruction decoder;
• a controller;
• and
• the input and output interface including a chip select pin;
• wherein, in standby state, the instruction decoder, the memory cell array, the input and output interface and the controller are enabled;
• in power-down state, the instruction decoder is enabled, and in deep power-down state, the instruction decoder and the controller are disabled;
• in response to the chip select pin receiving a chip select signal, the memory enters the power-down state from the deep power-down state;
• in response to the instruction decoder receiving a power-down state instruction, the memory enters the power-down state from the standby state;
• and in response to the instruction decoder receiving a deep power-down state instruction, the memory enters the deep power-down state from the standby state or power-down state.