Queues for inter-pipeline data hazard avoidance

A queue for use in a parallel processing unit wherein each instruction is related to a task of a plurality of tasks and data hazards are tracked using a plurality of counters, the queue comprising:

• a first-in-first-out queue configured to receive instructions output by an instruction decoder of the parallel processing unit to be executed by an instruction pipeline of the parallel processing unit, store the instructions in the order in which they were received, and output the received instructions in a same order;
• a hazard instruction queue configured to store hazard instructions in the order they are received until all hazards associated with a hazard instruction have been resolved;
• hazard detection logic configured to determine whether an instruction output from the first-in-first-out queue is a hazard instruction by:
• determining whether there is at least one instruction in the hazard instruction queue that is related to a same task as the instruction;
• in response to determining that there is at least one instruction in the hazard instruction queue that is related to the same task as the instruction, storing the instruction in the hazard instruction queue;
• if the instruction is a secondary instruction that is dependent on one or more primary instructions, determining whether a counter associated with at least one of the one or more primary instructions from which the secondary instruction depends indicates that a hazard related to the corresponding primary instruction has not been resolved;
• in response to determining that a counter associated with at least one primary instruction from which the secondary instruction depends indicates that the hazard related to the corresponding primary instruction has not been resolved, storing the instruction in the hazard instruction queue;
• otherwise output the instruction;
• and
• a multiplexor configured to select one of an instruction output by the hazard instruction queue and an instruction output by the hazard detection logic to forward to the instruction pipeline for execution.