Back to results
US 11,698,756 B2Granted
Cache-based memory read commands
AssigneeMicron Technology, Inc.
InventorsDhawal Bavishi, Patrick A. La Fratta
Life of this patent
Estimating the term…
Abstract
Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.
Claims20
A method comprising:
- receiving, at a memory controller device, a memory request to read data from a specified memory address of a memory sub-system, the memory controller device comprising a memory device to store one or more memory addresses associated with one or more past memory sub-system commands sent to the memory sub-system;
- and
- in response to determining that the specified memory address is currently stored in the memory device:
- accessing, from the memory device, a timestamp stored in association with the specified memory address;
- determining whether a current time is greater than a sum of the timestamp and an average read latency time of the memory sub-system;
- in response to the current time being greater than the sum, determining that there is a likelihood that data from the specified memory address is currently stored on a cache of the memory sub-system;
- and
- sending, by the memory controller device to the memory sub-system, at least one of a cache-based memory sub-system command for the specified memory address or a non-cache-based memory sub-system command for the specified memory address in response to determining that that there is the likelihood.
5 more elements
A system comprising:
- a processing device;
- and
- a memory controller device for processing memory requests generated by the processing device, the memory controller device comprising:
- a memory device to store one or more memory addresses associated with one or more past memory sub-system commands sent to a memory sub-system;
- and
- logic that performs operations comprising:
- receiving a memory request to read data from a specified memory address of the memory sub-system;
- and
- in response to determining that the specified memory address is currently stored in the memory device:
- accessing, from the memory device, a timestamp stored in association with the specified memory address;
- determining whether a current time is greater than a sum of the timestamp and an average read latency time of the memory sub-system;
- in response to the current time being greater than the sum, determining that there is a likelihood that data from the specified memory address is currently stored on a cache of the memory sub-system;
- and
- sending, to the memory sub-system, at least one of a cache-based memory sub-system command for the specified memory address or a non-cache-based memory sub-system command for the specified memory address in response to determining that that there is the likelihood.
11 more elements
A memory controller device comprising:
- a hardware interface for receiving a memory request;
- a memory device to store one or more memory addresses associated with one or more past memory sub-system commands sent to a memory sub-system;
- and
- logic that performs operations comprising:
- receiving, by the hardware interface, a memory request to read data from a specified memory address of the memory sub-system;
- and
- in response to determining that the specified memory address is currently stored in the memory device:
- accessing, from the memory device, a timestamp stored in association with the specified memory address;
- determining whether a current time is greater than a sum of the timestamp and an average read latency time of the memory sub-system;
- in response to the current time being greater than the sum, determining that there is a likelihood that data from the specified memory address is currently stored on a cache of the memory sub-system;
- and
- sending, to the memory sub-system, at least one of a cache-based memory sub-system command for the specified memory address or a non-cache-based memory sub-system command for the specified memory address in response to determining that that there is the likelihood.
9 more elements
Dependencies are inferred from the claim text.