Data storage device and method for low-latency power state transitions by having power islanding in a host memory buffer
AssigneeWestern Digital Technologies, Inc.
InventorsDinesh Kumar Agarwal, Amit Sharma
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AssigneeWestern Digital Technologies, Inc.
InventorsDinesh Kumar Agarwal, Amit Sharma
Estimating the term…
A data storage device and method for low-latency power state transitions by having power islanding in a host memory buffer are provided. In one embodiment, a data storage device is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to receive information from a host about which area, if any, in a host memory buffer will be powered on during a low-power state; and in response to the information indicating that a first area of the host memory buffer will be powered on during the low-power state, flush data from a second area of the host memory buffer that will not be powered on during the low-power state to the first area of the host memory buffer prior to entering the low-power state. Other embodiments are provided.
A data storage device comprising:
A method comprising:
A data storage device comprising:
Dependencies are inferred from the claim text.