US 11,698,673 B2 · Techniques for memory access in a reduced power state

Abstract

Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.

Claims25

Dependent claims

An apparatus, comprising:

a processor comprising one or more cores;
and
memory comprising a first memory portion and a second memory portion, the first memory portion comprising instructions that when executed by the processor cause the processor to:
identify one or more low-power mode blocks in a set of functional blocks of a computer, the computer comprising the processor, the memory, a first memory channel and a second memory channel, the first memory channel and the second memory channel to communicatively couple the processor with the second memory portion, the first memory channel and the second memory channel associated with a first address range and a second address range, respectively, wherein the first address range is different from the second address range;
and
map usage of the one or more low-power mode blocks in the set of functional blocks to the first address range associated with the first memory channel.

3 more elements

At least one non-transitory computer-readable medium comprising a set of instructions that, in response to being executed by a processor circuit, cause the processor circuit to:

identify one or more low-power mode blocks in a set of functional blocks of a computer, the computer comprising a processor with one or more cores, a memory, and first and second memory channels to communicatively couple the processor with the memory, the first memory channel and the second memory channel associated with a first address range and a second address range, respectively, wherein the first address range is different from the second address range;
and
map usage of the one or more low-power mode blocks in the set of functional blocks to a first address range associated with the first memory channel.

Dependencies are inferred from the claim text.

Techniques for memory access in a reduced power state

Life of this patent

Techniques for memory access in a reduced power state

Life of this patent

Abstract

Claims25