Integrated circuit and operating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsJieun Ahn, Sungcheol Park, Kiseok Bae
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Abstract
Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.
Claims20
An integrated circuit comprising:
- a plurality of clock generators configured to respectively generate a plurality of clock signals;
- a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals;
- and
- controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one of the plurality of clock generators so that the at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.
A method performed by an integrated circuit comprising a plurality of clock generators, the method comprising:
- identifying a first clock signal from a plurality of clock signals and a second clock signal from the plurality of clock signals, the first clock signal and the second clock signal causing meta-stability based on frequencies of the plurality of clock signals generated by the plurality of clock generators;
- delaying randomly at least one of the first clock signal and the second clock signal;
- and
- providing the first clock signal to a first logic circuit and the second clock signal to a second logic circuit,
- wherein the first logic circuit communicates with the second logic circuit in synchronization with the first clock signal, and the second logic circuit communicates with the first logic circuit in synchronization with the second clock signal.
A method performed by an integrated circuit comprising a plurality of clock generators, the method comprising:
- identifying a clock generator causing meta-stability in logic circuits that communicate with each other, the identifying based on frequencies of clock signals of each of the plurality of clock generators;
- selecting at least one clock generator, which randomly delays a clock signal, from the identified clock generator;
- and
- providing a random delay to the logic circuit via the selected at least one clock generator.
Dependencies are inferred from the claim text.