US 11,698,658 B1Granted

Skew-correcting clock buffer

AssigneeAcacia Communications, Inc.

InventorsGavin Allen, Ian Dedic, Bo Yang, Tarun Gupta

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Abstract

A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.

Claims20

Dependent claims

An apparatus comprising:

a first CMOS inverter stage paired with a first non-inverting push-pull source follower stage;
wherein a clock bar signal is connected to the first non-inverting push-pull source follower stage and an inverse of a clock signal is connected to the first CMOS inverter stage such that inverse of the clock signal is combined with the clock bar signal to form a clock bar out signal;
further wherein the clock bar signal and the inverse of the clock signal contribute equally to forming the clock bar out signal;
and
a second CMOS inverter stage paired with a second non-inverting push-pull source follower stage;
wherein the clock signal is connected to the second non-inverting push-pull source follower stage and the inverse of the clock bar signal is connected to the second CMOS inverter stage such that inverse of the clock bar signal is combined with the clock signal to form a clock out signal;
further wherein the clock signal and the inverse of the clock bar signal contribute equally to forming the clock out signal.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/833,306Filed 6 Jun 2022 · continuation
Priority: 20 Feb 2020
Granted: 11 Jul 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
H03K 5/1565
Arrangements in which a continuous pulse train is transformed into a train having a desired pattern: the output pulses having a constant duty cycle
H03K 3/037
By the use of logic circuits, with internal or external positive feedback: bistable circuits
G06F
Computing and data processing