Fractional clock divider

A clock divider circuit configured to generate an output clock signal having a fundamental frequency which is substantially equal to a fundamental frequency of an input clock signal divided by a factor of (2N+1)/2N, wherein N is an integer, and wherein the clock divider circuit comprises:

• a divide by 2N+1 circuit configured to generate 2(2N+1) intermediate phase shifted clock signals;
• a multiply by 2 circuit configured to receive the 2(2N+1) intermediate phase shifted clock signals and to generate 2N+1 pre-aligned phase shifted clock signals based at least in part on the received 2(2N+1) intermediate phase shifted clock signals;
• a phase adjust circuit configured to receive the 2N+1 pre-aligned phase shifted clock signals and to generate 2N unique phase shifted clock signals based at least in part on the received 2N+1 pre-aligned phase shifted clock signals, wherein the 2N unique phase shifted clock signals are substantially separated in phase by 360/2N degrees;
• and
• a multiply by 2N/2 circuit configured to receive the 2N unique phase shifted clock signals and to generate the output clock signal based at least in part on the received 2N unique phase shifted clock signals.

A method of operating a communication circuit, the method comprising:

• with a clock divider circuit, generating an output clock signal having a fundamental frequency which is substantially equal to a fundamental frequency of an input clock signal divided by a factor of (2N+1)/2N, wherein N is an integer, and wherein generating the output clock signal comprises:
• generating 2N+1 pre-aligned phase shifted clock signals based at least in part on the input clock signal,
• generating 2N unique phase shifted clock signals based at least in part on the 2N+1 pre-aligned phase shifted clock signals, wherein the 2N unique phase shifted clock signals are substantially separated in phase by 360/2N degrees, and
• generating the output clock signal based at least in part on the 2N unique phase shifted clock signals;
• and
• with a mixer, receiving the output clock signal.