System, device and method for generating a biasing current

A system, comprising:

• a first stage having a current bias generator that generates a biasing current, the current bias generator including a resistor structure that comprises an emulated resistor;
• a second stage coupled to the first stage, wherein the second stage has a load that utilizes the biasing current generated by the current bias generator;
• and
• a reference voltage generator that generates a reference voltage,
• wherein the reference voltage generator includes a first native device structure and a first plurality of stacking transistor structures that are coupled in series between the supply voltage and ground,
• wherein the first native device structure includes a gate that is coupled between a first transistor and a second transistor of the first plurality of stacking transistor structures,
• wherein the resistor structure has a second plurality of stacking transistor structures coupled in series,
• wherein the current bias generator has a native device structure with a gate coupled to ground,
• wherein the resistor structure of the current bias generator is coupled between a source terminal of the native device structure and ground, and
• wherein the reference voltage is used to activate the second plurality of stacking transistor structures.

A device, comprising:

• a first native device structure that is configured to receive a supply voltage, wherein the first native device structure has a gate coupled to ground;
• a resistor structure comprising an emulated resistor coupled between the native device structure and ground, wherein the first native device structure and the resistor structure are configured to generate a biasing current for a load;
• and
• a reference voltage generator that generates a reference voltage,
• wherein the reference voltage generator includes a second native device structure and a first plurality of stacking transistor structures that are coupled in series between the supply voltage and ground,
• wherein the second native device structure includes a gate that is coupled between a first transistor and a second transistor of the first plurality of stacking transistor structures,
• wherein the resistor structure has a second plurality of stacking transistor structures coupled in series, and
• wherein the reference voltage is used to activate the first plurality of stacking transistor structures.

A method, comprising:

• coupling a gate of a first native device structure to ground;
• coupling a resistor structure between the first native device structure and ground, the resistor structure comprising an emulated resistor;
• coupling a load to the first native device structure;
• generating a biasing current for the load with the first native device structure and the resistor structure;
• and
• generating a reference voltage with a reference voltage generator,
• wherein the reference voltage generator includes a second native device structure and a first plurality of stacking transistor structures that are coupled in series between a supply voltage and ground,
• wherein the second native device structure includes a gate that is coupled between a first transistor and a second transistor of the first plurality of stacking transistor structures,
• wherein the resistor structure has a second plurality of stacking transistor structures coupled in series, and
• wherein the reference voltage is used to activate the second plurality of stacking transistor structures.

A method, comprising:

• coupling a gate of a first native device structure to ground;
• coupling a resistor structure between the first native device structure and ground, the resistor structure comprising an emulated resistor;
• coupling a load to the first native device structure;
• generating a biasing current for the load with the first native device structure and the resistor structure;
• and
• generating a reference voltage with a reference voltage generator,
• wherein the reference voltage generator includes a second native device structure and a first plurality of stacking transistor structures that are coupled in series between a supply voltage and ground,
• wherein the second native device structure includes a gate that is coupled between a first transistor and a second transistor of the first plurality of stacking transistor structures,
• wherein the resistor structure has a second plurality of stacking transistor structures coupled in series,
• wherein the resistor structure is coupled between a source terminal of the native device structure and ground, and
• wherein the reference voltage is used to activate the second plurality of stacking transistor structures.