Self-test circuit for an integrated circuit, and method for operating a self-test circuit for an integrated circuit

A self-test circuit for an integrated circuit, comprising:

• a plurality of scan chains, each scan chain comprising:
• a plurality of first memory elements;
• a data input for providing the scan chain with test data, wherein the data input is connected to one of the first memory elements of the scan chain;
• a plurality of second memory elements;
• a switching apparatus having a first switching position and a second switching position, the switching apparatus being coupled between the first memory elements and the second memory elements, and the switching apparatus being configured, when the integrated circuit is in a first mode, to connect a last one of the first memory elements to a data output in the first switching position and configured, when the integrated circuit is in a second mode, to connect the last one of the first memory elements to a first one of the second memory elements in the second switching position;
• and
• a logic circuit which is coupled to the data outputs of the plurality of scan chains, wherein the logic circuit is configured to logically combine output data from only the first memory elements of the plurality of scan chains.