Vertical metal oxide semiconductor channel selector transistor and methods of forming the same

A method of forming a device structure, comprising:

• forming dielectric material layers over a substrate;
• forming a via-level dielectric layer over the dielectric material layers;
• forming vertical stacks of a respective bottom electrode, a respective metal oxide semiconductor channel material layer, and a respective top electrode over the via-level dielectric layer;
• and
• forming a gate dielectric layers and gate electrodes on sidewalls of the vertical stacks, wherein:
• each of the gate dielectric layers is formed on a sidewall of a respective one of the vertical stacks;
• each of the gate electrodes is formed within a volume that is laterally surrounded by a respective one of the gate dielectric layers;
• and
• top surfaces of the gate electrodes are formed within a same horizontal plane as top surfaces of the top electrodes within the vertical stacks.

A method of forming a device structure, comprising:

• forming vertical stacks of a respective bottom electrode, a respective metal oxide semiconductor channel material layer, and a respective top electrode over the via-level dielectric layer over a substrate, wherein the vertical stacks are laterally spaced apart along a first horizontal direction;
• forming gate dielectric layers and gate electrodes, wherein each of the gate dielectric layers is formed on a sidewall of a respective one of the vertical stacks, each of the gate electrodes is formed within a volume that is laterally surrounded by a respective one of the gate dielectric layers;
• forming two rows of non-volatile memory elements over each of the vertical stacks, wherein each row of non-volatile memory elements is arranged along a second horizontal direction that is different from the first horizontal direction;
• forming a memory-level dielectric layer over the non-volatile memory elements;
• and
• forming dielectric isolation structures through the vertical stacks, wherein each of the vertical stacks is divided into a respective pair of rows of series connections of a vertical field effect transistor and a non-volatile memory element,
• wherein the dielectric isolation structures cuts through each of the gate electrodes, wherein each of the gate electrodes is divided into multiple divided gate electrodes that are arranged along the second horizontal direction.