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US 11,696,452 B2Granted
Multi-level memristor elements
AssigneeCirrus Logic, Inc.
InventorsJohn Paul Lesso, Gordon James Bates
Life of this patent
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Abstract
There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.
Claims20
A two-terminal multi-level memristor comprising:
- a first set of resistance elements comprising a plurality of resistance elements connected in series between first and second terminals of the multi-level memristor;
- and
- a second set of resistance elements comprising a plurality of second resistance elements, wherein each of the resistance elements of the second set is connected in parallel with a different number of one or more of the series connected resistance elements of the first set,
- wherein one of the first set and second set of resistance elements comprises a plurality of binary memristors that can be selectively programmed to either a high or low resistance state and the other of the first and second set of resistance elements comprises a plurality of shunt resistors.
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A two-terminal multi-level memristor element comprising:
- a plurality of first resistance elements connected in series between first and second terminals of the multi-level memristor element;
- and
- a plurality of second resistance elements, wherein each of the second resistance elements is connected in parallel with a different number of one or more of the series connected first resistance elements,
- wherein one of the first and second resistance elements comprise binary memristors that can be selectively programmed to either a high or low resistance state and the other of the first and second resistance elements comprise shunt resistors.
1 more element
A two-terminal memristor apparatus which is programmable to provide more than two different define resistance values between the two terminals, the apparatus comprising:
- a first set of a plurality of resistance elements connected in series between the two terminals of the multi-level memristor apparatus;
- and
- a second set of a plurality of resistance elements which are nested in parallel with different numbers of resistance elements of the first set,
- wherein at least some of the resistance elements of the first and second sets comprise binary memristors that can be selectively programmed to either a high or low resistance state and at least some of the resistance elements of the first and second sets comprise non-programmable resistors.
1 more element
Dependencies are inferred from the claim text.