US 11,696,449 B2 · Semiconductor devices and methods of manufacturing thereof

Abstract

A semiconductor die comprises a device portion comprising: an array of active memory devices extending in a first direction, and interface portions located adjacent to axial ends of the device portion in the first direction. The interface portions have a staircase profile in a vertical direction and comprise an array of dummy memory devices and an array of gate vias. The dummy memory devices are axially aligned with the active memory devices in the first direction, each dummy memory device comprising at least one interface via. Moreover, each row of the array of gate vias extends in the first direction and is located parallel to a row of the array of dummy memory devices in a second direction perpendicular to the first direction. Each gate via is electrically coupled to the at least one interface via of a dummy memory device located adjacent thereto.

Claims17

Dependent claims

A semiconductor die, comprising:

a device portion, comprising:
an array of active memory devices, each row of the array of active memory devices extending in a first direction;
and
at least one interface portion located adjacent to an axial end of the device portion in the first direction, the at least one interface portion having a staircase profile in a vertical direction, the at least one interface portion comprising:
an array of dummy memory devices, each row of the array of dummy memory devices axially aligned with a corresponding row of the array of active memory devices in the first direction, each dummy memory device comprising at least one interface via;
and
an array of gate vias, each row of the array of gate vias extending in the first direction and located parallel to a row of the array of dummy memory devices in a second direction perpendicular to the first direction, each gate via being electrically coupled to the at least one interface via of a dummy memory device located adjacent thereto.

4 more elements

A semiconductor die, comprising:

a device portion, comprising:
an array of active memory devices, each row of the array of active memory devices extending in a first direction, wherein each active memory device comprises:
a source,
a drain spaced apart from the source in the first direction,
a channel layer disposed on radially outer surfaces of the source and the drain, the channel layer extending in the first direction,
a memory layer disposed on a radially outer surface of the channel layer and extending in the first direction, and
a stack disposed on outer surfaces of the memory layer and extending in the first direction, the stack comprising a plurality of insulating layers and a plurality of gate layers alternatively stacked on top each other;
and
at least one interface portion located adjacent to an axial end of the device portion in the first direction, the at least one interface portion having a staircase profile in a vertical direction, the at least one interface portion comprising:
an array of dummy memory devices, each row of the array of dummy memory devices axially aligned with a corresponding row of the array of active memory devices in the first direction,
wherein, the memory layer extends from the device portion to the at least one interface portion along the respective row of active memory devices to a corresponding row of the array of dummy memory devices, the memory layer being continuous from the device portion to the at least one interface portion.

8 more elements

Dependencies are inferred from the claim text.

Semiconductor devices and methods of manufacturing thereof

Life of this patent

Semiconductor devices and methods of manufacturing thereof

Life of this patent

Abstract

Claims17