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US 11,696,438 B2Granted
Compact EEPROM memory cell with a gate dielectric layer having two different thicknesses
AssigneeSTMicroelectronics (Rousset) SAS
InventorFrançois Tailliet
Life of this patent
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Abstract
An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.
Claims20
A method of making an electrically erasable and programmable non-volatile memory device, the method comprising:
- forming a first dielectric layer over a surface of a semiconductor substrate, the first dielectric layer having a first thickness;
- removing a portion of the first dielectric layer to form an opening;
- forming a second dielectric layer over the first dielectric layer and the opening, the second dielectric layer having a second thickness less than the first thickness;
- forming a floating gate and a first access gate over the semiconductor substrate, a first portion of the floating gate overlying the first dielectric layer and a second portion of the floating gate overlying the second dielectric layer in the opening, the first access gate overlying the first dielectric layer and spaced from the floating gate by a remaining portion of the opening;
- forming a control gate dielectric layer over the semiconductor substrate;
- forming a second gate layer over the control gate dielectric layer;
- etching a portion of the second gate layer down to the second dielectric layer to form a control gate that overlies the floating gate and to also form a second access gate that overlies the first access gate, the control gate having a first thickness in a first region overlying a portion of the first dielectric layer and having a second thickness in a second region overlying a portion of the second dielectric layer, the second thickness being greater than the first thickness;
- and
- implanting dopants into the surface of the substrate to form a drain region of a state transistor, a source region of an access transistor, and a common region that serves as a source region of the state transistor and a drain region of the access transistor, the state transistor including the floating gate and the control gate and the access transistor including the first access gate and the second access gate.
6 more elements
A method of making an electrically erasable and programmable non-volatile memory device, the method comprising:
- forming a plurality of bit lines and a plurality of source lines;
- and
- forming a memory plane including a plurality of memory cells, each memory cell comprising a state transistor having a source region, a drain region, a control gate and a floating gate, each memory cell also comprising an access transistor having a source region, a drain region and a gate;
- wherein the source region of each access transistor is coupled to a source line of the plurality of source lines;
- wherein the drain region of the access transistor and the source region of the state transistor are common;
- wherein the drain region of each state transistor is coupled to a bit line of the plurality of bit lines;
- and
- wherein the floating gate of each memory cell overlies a dielectric layer having a first part with a first thickness and a second part with a second thickness that is less than the first thickness, the second part being located on a source region side of the state transistor, wherein the dielectric layer includes a further third part extending beyond the floating gate, located above and overlapping with the source region of the state transistor and having a third thickness that is equal to the second thickness.
5 more elements
A method of making an electrically erasable and programmable non-volatile memory device, the method comprising:
- forming a floating gate transistor comprising a source region, a drain region, a first dielectric layer, a control gate, a second dielectric layer, and a floating gate, the first dielectric layer being formed between a surface of a semiconductor substrate and the floating gate, the second dielectric layer being formed between the floating gate and the control gate, the first dielectric layer having a first part with a first thickness and a second part with a second thickness that is less than the first thickness, the second part being formed directly over the source region of the floating gate transistor, the floating gate having a substantially uniform thickness, the drain region of the floating gate transistor being coupled to a bit line of a plurality of bit lines, wherein the control gate comprises a first region with a third thickness overlaying a portion of the first part of the first dielectric layer and a second region with a fourth thickness overlaying the second part of the first dielectric layer, the fourth thickness being larger than the third thickness;
- and
- forming an access transistor having a source region, a drain region and a gate, the drain region of the access transistor and the source region of the floating gate transistor sharing a common region, wherein the source region of the access transistor is coupled to a source line of a plurality of source lines.
Dependencies are inferred from the claim text.