Integrated circuit device

An integrated circuit (IC) device comprising:

• first through fourth device pairs positioned in corresponding first through fourth active areas extending in a first direction, wherein
• each device pair comprises a first transistor coupled between a first anti-fuse structure and a shared bit line contact, and a second transistor coupled between a second anti-fuse structure and the shared bit line contact,
• each of the first and third active areas is adjacent to the second active area along a second direction perpendicular to the first direction, and
• the fourth active area is adjacent to the third active area along the second direction;
• first through fourth conductive lines extending in the second direction;
• a first conductive path configured to couple the second conductive line to the first transistor of each device pair;
• second and third conductive paths, each configured to couple the first conductive line to the first anti-fuse structure of each device pair;
• fourth and fifth conductive paths, each configured to couple the fourth conductive line to the second anti-fuse structure of each device pair;
• and
• a sixth conductive path configured to couple the third conductive line to the second transistor of each device pair,
• wherein
• the first and fourth conductive paths are aligned with each other along the first direction and positioned between the first and second active areas,
• the second and fifth conductive paths are aligned with each other along the first direction and positioned between the second and third active areas, and
• the third and sixth conductive paths are aligned with each other along the first direction and positioned between the third and fourth active areas.

An anti-fuse array comprising:

• a column of anti-fuse bit pairs positioned in corresponding active areas extending in a row direction;
• and
• first through fourth conductive lines extending along the column of anti-fuse bit pairs,
• wherein
• the first conductive line is electrically connected to a first anti-fuse structure of each anti-fuse bit pair of the column,
• the second conductive line is electrically connected to a first transistor of each anti-fuse bit pair of the column,
• the third conductive line is electrically connected to a second transistor of each anti-fuse bit pair of the column,
• the fourth conductive line is electrically connected to a second anti-fuse structure of each anti-fuse bit pair of the column, and
• each region between adjacent active areas of the column of anti-fuse bit pairs comprises:
• a first conductive path configured to couple one of the first or second conductive lines to the corresponding first anti-fuse structures or first transistors of the column;
• and
• a second conductive path configured to couple one of the third or fourth conductive lines to the corresponding second transistors or second anti-fuse structures of the column.