Two-port SRAM structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
An integrated circuit structure includes a Static Random Access Memory (SRAM) cell, which includes a read port and a write port. The write port includes a first pull-up Metal-Oxide Semiconductor (MOS) device and a second pull-up MOS device, and a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. The integrated circuit structure further includes a first metal layer, with a bit-line, a CVdd line, and a first CVss line in the first metal layer, a second metal layer over the first metal layer, and a third metal layer over the second metal layer. A write word-line is in the second metal layer. A read word-line is in the third metal layer.
Claims20
An integrated circuit structure comprising:
- a Static Random Access Memory (SRAM) cell comprising a read port and a write port;
- a first metal layer, with a bit-line, a CVdd line, and a CVss line in the first metal layer and in the SRAM cell;
- a second metal layer over the first metal layer, wherein a write word-line is in the second metal layer and overlaps the SRAM cell, and the write word-line is connected to the write port, wherein the second metal layer has a first thickness;
- and
- a third metal layer over the second metal layer, wherein the third metal layer has a second thickness smaller than the first thickness, and wherein a read word-line is in the third metal layer and is connected to the read port.
An integrated circuit structure comprising:
- a plurality of Static Random Access Memory (SRAM) cells forming a row;
- a first word-line overlapping the plurality of SRAM cells;
- and
- a second word-line overlapping the first word-line and the plurality of SRAM cells, wherein the first word-line and the second word-line are configured to have different voltages, and wherein in a cross-sectional view of the integrated circuit structure, the first word-line is thicker than the second word-line.
An integrated circuit structure comprising:
- a Static Random Access Memory (SRAM) cell comprising:
- a first node and a second node;
- a first pass-gate transistor comprising a first source/drain region connected to the first node;
- a second pass-gate transistor comprising a second source/drain region connected to the second node;
- a read pull-down transistor comprising a second gate connected to the first node;
- and
- a third pass-gate transistor comprising a third source/drain region connected to a fourth source/drain region of the read pull-down transistor;
- a write word-line electrically connected to first gates of the first pass-gate transistor and the second pass-gate transistor, wherein the write word-line is in a first metal layer;
- and
- a read word-line electrically connected to a fourth gate of the third pass-gate transistor, wherein the read word-line is in a second metal layer higher than the first metal layer, and the read word-line is thinner and wider than the write word-line.
Dependencies are inferred from the claim text.