Reduced overhead error detection code design for decoding a codeword

A method for wireless communication, comprising:

• processing a signal comprising a codeword to obtain a candidate bit sequence;
• segmenting the candidate bit sequence into a first code block and a second code block;
• identifying a first segment comprising a first number of information bits of the first code block using a first error detection code (EDC) comprising a first number of error detection bits;
• identifying a second segment comprising a second number of information bits different from the first number of information bits of the second code block using a second EDC comprising a second number of error detection bits different from the first number of error detection bits;
• and
• generating control data from the first segment and the second segment.

An apparatus for wireless communication, comprising:

• a processor;
• and
• memory coupled with the processor and storing instructions executable by the processor to cause the apparatus to:
• segment control information into a first segment and a second segment, wherein a number of information bits of the first segment is different from a number of information bits of the second segment;
• generate a first error detection code (EDC) for the first segment including a first number of error detection bits;
• generate a second EDC for the second segment including a second number of error detection bits different from the first number of error detection bits;
• polar encode the first segment, the first EDC, the second segment, and the second EDC;
• and
• transmit a transmission based at least in part on the polar encoding via a wireless channel.

An apparatus for wireless communication, comprising:

• a processor;
• and
• memory coupled with the processor and storing instructions executable by the processor to cause the apparatus to:
• process a signal comprising a codeword to obtain a candidate bit sequence;
• segment the candidate bit sequence into a first code block and a second code block;
• identify a first segment comprising a first number of information bits of the first code block using a first error detection code (EDC) comprising a first number of error detection bits;
• identify a second segment comprising a second number of information bits different from the first number of information bits of the second code block using a second EDC comprising a second number of error detection bits different from the first number of error detection bits;
• and
• generate control data from the first segment and the second segment.