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US 11,695,432 B2Granted
Apparatus for transmitting data in interleave division multiple access (IDMA) system
AssigneeSony Group Corporation
InventorsRyota Kimura, Yifu Tang
Life of this patent
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Abstract
There is provided an apparatus including an acquisition unit that acquires an information block generated from transmission data for a user and subjected to error correction coding, and an interleaving unit that interleaves a bit sequence of the information block using an interleaver unique to the user. The interleaving unit interleaves the bit sequence by interleaving each of two or more partial sequences obtained from the bit sequence.
Claims16
An apparatus, comprising:
- circuitry configured to interleave a bit sequence of an information block based on interleave of each of a plurality of partial sequences obtained from the bit sequence, wherein
- the information block is subjected to an error correction coding operation, and
- a length of each of the plurality of partial sequences is a power of two.
An apparatus, comprising:
- circuitry configured to:
- acquire a bit sequence;
- and
- generate an information block by de-interleave of the acquired bit sequence based on a de-interleaver, wherein
- the de-interleaver corresponds to an interleaver unique to a user,
- the de-interleave of the acquired bit sequence is by de-interleave of each of a plurality of partial sequences obtained from the acquired bit sequence,
- each of the plurality of partial sequences is included in the acquired bit sequence,
- a first partial sequence of the plurality of partial sequences is in a non-overlapping arrangement with a second partial sequence of the plurality of partial sequences,
- the information block is non-decoded for error correction, and
- a length of each of the plurality of partial sequences is a power of two.
7 more elements
A method, comprising:
- interleaving a bit sequence of an information block based on interleave of each of a plurality of partial sequences obtained from the bit sequence, wherein
- the information block is subjected to an error correction coding operation, and
- a length of each of the plurality of partial sequences is a power of two.
An apparatus, comprising:
- circuitry configured to interleave a bit sequence of an information block based on interleave of each of a plurality of partial sequences obtained from the bit sequence, wherein
- the information block is subjected to an error correction coding operation,
- a length of each of the plurality of partial sequences is a power of two,
- each of the plurality of partial sequences is included in the bit sequence, and
- a first partial sequence of the plurality of partial sequences is in a non-overlapping arrangement with a second partial sequence of the plurality of partial sequences.
2 more elements
Dependencies are inferred from the claim text.