ADC slicer reconfiguration for different channel insertion loss
AssigneeeTopus Technology Inc.
InventorDanfeng Xu
Life of this patent
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Abstract
A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the insertion loss mode of the receiver. For example, different portions of a plurality of time-interleaved successive approximation (SAR) ADC slices included in at least one sub-ADC of each time-interleaved ADC may be enabled depending on which of a plurality of insertion loss modes is selected for operation of the receiver.
Claims20
A receiver comprising:
- a clock generator including a plurality of clock signal generators that generate a plurality of sampling clock signals having a plurality of sampling phases, each of the plurality of sampling clock signals having a corresponding one of the plurality of sampling phases;
- and
- a plurality of time-interleaved analog-to-digital converters (ADC) that each sample an analog input signal at a corresponding one of the plurality of sampling phases to convert the analog signal into a digital sample, each of the plurality of time-interleaved ADCs including a plurality of sub-ADCs that sample the analog input signal at a data rate of the receiver;
- wherein responsive to the receiver being configured to operate at an insertion loss mode from a plurality of insertion loss modes where the insertion loss mode has an insertion loss that is less than a maximum insertion loss of the receiver, a part of each sub-ADC of the plurality of sub-ADCs of at least one of the plurality of time-interleaved ADCs is enabled to sample the analog input signal at the data rate of the receiver to generate the digital sample and a remaining part of each-sub-ADC of the plurality sub-ADCs of the at least one of the plurality of time-interleaved ADCs is disabled,
- wherein during the insertion loss mode the receiver is configured to convert the analog signal into the digital sample such that the digital sample has the insertion loss associated with the insertion loss mode.
A method of a receiver that includes a clock generator and a plurality of time-interleaved analog-to-digital converters (ADC) comprising a plurality of sub-ADCs that sample the analog input signal at a data rate of the receiver, the method comprising:
- generating a plurality of sampling clock signals having a plurality of sampling phases, each of the plurality of sampling clock signals having a corresponding one of the plurality of sampling phases;
- and
- sampling the analog input signal using each of the plurality of time-interleaved ADCs, the analog input signal sampled by each of the plurality of time-interleaved ADCs at a corresponding one of the plurality of sampling phases to convert the analog signal into a digital sample;
- wherein responsive to the receiver being configured to operate at an insertion loss mode from a plurality of insertion loss modes where the insertion loss mode has an insertion loss that is less than a maximum insertion loss of the receiver, enabling a part of each sub-ADC of the plurality of sub-ADCs of at least one of the plurality of time-interleaved ADCs to sample the analog input signal at the data rate of the receiver to generate the digital sample and disabling a remaining part of each sub-ADC of the plurality sub-ADCs of the at least one of the plurality of time-interleaved ADCs,
- wherein during the insertion loss mode the receiver is configured to convert the analog signal into the digital sample such that the digital sample has the insertion loss associated with the insertion loss mode.
Dependencies are inferred from the claim text.