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US 11,695,422 B2Granted
Delay line, a delay locked loop circuit and a semiconductor apparatus using the delay line and the delay locked loop circuit
AssigneeSK hynix Inc.
InventorsYun Tack Han, Kyeong Min Kim
Life of this patent
Estimating the term…
Abstract
A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.
Claims13
A delay locked loop circuit comprising:
- a voltage-controlled delay line configured to delay a reference clock signal based on a delay control voltage to generate an internal clock signal and a feedback clock signal;
- a calibration circuit configured to delay the internal clock signal and the feedback clock signal to generate a delayed reference clock signal and a delayed feedback clock signal, and to change delay amount of the internal clock signal and delay amount of the feedback clock signal according to phases of the internal clock signal and the feedback clock signal;
- a phase detector configured to compare phases between the delayed reference clock signal and the delayed feedback clock signal to generate a phase detection signal;
- and
- a charge pump configured to generate the delay control voltage based on the phase detection signal.
2 more elements
A delay locked loop circuit comprising:
- a voltage-controlled delay line configured to delay a reference clock signal based on a delay control voltage to generate an internal clock signal and a feedback clock signal;
- a calibration circuit configured to generate a calibration signal based on the internal clock signal and the feedback clock signal, and to delay the internal clock signal and the feedback clock signal based on the calibration signal to generate a delayed reference clock signal and a delayed feedback clock signal;
- a phase detector configured to compare phases between the delayed reference clock signal and the delayed feedback clock signal to generate a phase detection signal;
- and
- a charge pump configured to generate the delay control voltage based on the phase detection signal.
2 more elements
Dependencies are inferred from the claim text.