Integrated circuit and method of manufacturing same

An integrated circuit, comprising:

• a first well extending in a first direction, being in a substrate, and having a first dopant type;
• a first set of transistors including a first set of active regions extending in the first direction, being on a first level, and in the first well;
• a second set of transistors including a second set of active regions outside of the first well, extending in the first direction, being on the first level, and being separated from the first set of active regions in a second direction different from the first direction;
• a first circuit having a first active region in the first well, and configured to supply a first voltage to a first transistor in the second set of transistors, a first transistor in the first set of transistors comprises:
• a first feedback transistor including a first gate extending in the second direction, a first source/drain (S/D) region of the first feedback transistor corresponding to a first portion of a first active region of the first set of active regions, and a second S/D region of the first feedback transistor corresponding to a second portion of the first active region of the first set of active regions;
• a second circuit having a second active region next to the second set of active regions, and configured to supply a second voltage to the first transistor in the first set of transistors;
• a first power rail extending in the first direction, being configured to supply the first voltage to at least the first circuit, the first power rail electrically connected to at least the first circuit, and being on a second level different from the first level;
• and
• a second power rail extending in the first direction, being separated from the first power rail in the second direction, being configured to supply the second voltage to at least the second circuit, the second power rail electrically connected to at least the second circuit, and being on the second level,
• wherein the first gate is on a third level different from the first level and the second level.

An integrated circuit, comprising:

• a first well extending in a first direction, being in a substrate, and having a first dopant type;
• a first set of transistors including a first transistor of a first type, and a first set of active regions extending in the first direction, and being on a first level, and in the first well;
• a second set of transistors including a second transistor of a second type, and a second set of active regions outside of the first well, extending in the first direction, being on the first level, and being separated from the first set of active regions in a second direction different from the first direction;
• a first circuit having a first active region in the first well, the first circuit includes:
• a third transistor of the first type, and being configured to supply a first voltage to the second transistor;
• a second circuit having a second active region next to the second set of active regions, the second circuit includes:
• a fourth transistor of the second type, the fourth transistor configured to supply a second voltage to the first transistor;
• a first power rail extending in the first direction, being configured to supply the first voltage to at least the third transistor, the first power rail being electrically connected to at least the third transistor, and being on a second level different from the first level;
• and
• a second power rail extending in the first direction, being separated from the first power rail in the second direction, being configured to supply the second voltage to at least the fourth transistor, the second power rail being electrically connected to at least the fourth transistor, and being on the second level;
• and
• a first gate structure extending in the second direction, overlapping the first well, being between the first set of active regions and the first active region, and being on a third level different from the first level and the second level.