Digital timer delay line with sub-sample accuracy
AssigneeDialog Semiconductor (UK) Limited
InventorMichael Kramer
Life of this patent
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Abstract
The present document relates to a timer which is counter-based and uses an asynchronous circuitry to improve the accuracy between the available clock cycles. In particular, a timer is presented which may comprise a first timer circuit configured to receive a clock signal and a trigger signal, wherein an edge of the trigger signal arrives after a first edge of the clock signal and before a second edge of the clock signal. The first timer circuit may be configured to determine, in a capture phase, a time offset interval for approximating a time interval between the first edge of the clock signal and the edge of the trigger signal.
Claims24
A timer comprising a first timer circuit configured to receive a clock signal and a trigger signal, wherein an edge of the trigger signal arrives after a first edge of the clock signal and before a second edge of the clock signal, and wherein the first timer circuit is configured to
- determine, in a capture phase, a time offset interval for approximating a time interval between the first edge of the clock signal and the edge of the trigger signal,
- generate, at the end of a count phase, an edge of an internal response signal at the end of a predetermined time interval measured from the second edge of the clock signal, and
- generate, at the end of a replay phase, an edge of a return signal at the end of the time offset interval measured from the edge of the internal response signal.
A method of operating a timer, wherein the timer comprises a first timer circuit for receiving a clock signal and a trigger signal, wherein an edge of the trigger signal arrives after a first edge of the clock signal and before a second edge of the clock signal, and wherein the method comprises:
- determining, in a capture phase, by the first timer circuit, a time offset interval for approximating a time interval between the first edge of the clock signal and the edge of the trigger signal,
- generating, at the end of a count phase, by the first timer circuit, an edge of an internal response signal at the end of a predetermined time interval measured from the second edge of the clock signal, and
- generating, at the end of a replay phase, by the first timer circuit, an edge of a return signal at the end of the time offset interval measured from the edge of the internal response signal.
Dependencies are inferred from the claim text.