Offset circuitry and threshold reference circuitry for a capture flip-flop
AssigneeXilinx, Inc.
InventorsWenfeng Zhang, Parag Upadhyaya
Life of this patent
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Abstract
Receiver circuitry for a communication system includes signal processing circuitry, voltage digital-to-analog converter (DAC) circuitry, and slicer circuitry. The signal processing circuitry receives a data signal and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage. The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage. The CapFF circuit further generates a first data signal. The first CapFF circuit includes a first offset compensation circuit that adjusts a parasitic capacitance of the first CapFF circuit.
Claims17
Receiver circuitry for a communication system, the receiver circuitry comprising:
- signal processing circuitry configured to receive a data signal and generate a processed data signal;
- voltage digital-to-analog converter (DAC) circuitry configured to generate a first threshold reference voltage;
- and
- slicer circuitry coupled to an output of the signal processing circuitry, the slicer circuitry comprising:
- a first capture flip-flop (CapFF) circuit configured to receive the processed data signal and the first threshold reference voltage and generate a first data signal, wherein the first CapFF circuit comprises a first offset compensation circuit comprising a first capacitor DAC (CDAC) connected to a first node of the first CapFF circuit and configured to apply a first parasitic capacitance to the first node, and a second CDAC connected to a second node of the first CapFF circuit and configured to apply a second parasitic capacitance to the second node.
A communication system comprising:
- transmitter circuitry configured to transmit a data signal;
- and
- receiver circuitry connected to the transmitter circuitry via a channel, the receiver circuitry comprising:
- signal processing circuitry configured to receive the data signal and generate a processed data signal;
- voltage digital-to-analog converter (DAC) circuitry configured to generate a first threshold reference voltage;
- and
- slicer circuitry coupled to an output of the signal processing circuitry, the slicer circuitry comprising:
- a first capture flip-flop (CapFF) circuit configured to receive the processed data signal and the first threshold reference voltage and generate a first data signal, wherein the first CapFF circuit comprises a first offset compensation circuit comprising a first capacitor (CDAC) connected to a first node of the first CapFF circuit and configured to apply a first parasitic capacitance to the first node, and a second CDAC connected to a second node of the first CapFF circuit and configured to apply a second parasitic capacitance to the second node.
A method for operating receiver circuitry, the method comprising:
- receiving a data signal and generating a processed data signal from the data signal;
- generating, via a voltage-to-analog convertor (DAC) circuitry, a first threshold reference voltage;
- receiving, at a first CapFF circuit the processed data signal and the first threshold reference voltage;
- applying, via a first capacitor DAC (CDAC) of a first offset compensation circuit of the first CapFF circuit, a first parasitic capacitance to a first node of the first CapFF circuit;
- applying, via a second CDAC of the first offset compensation circuit, a second parasitic capacitance to a second node of the first CapFF circuit;
- and
- generating an output signal from the processed data signal.
Dependencies are inferred from the claim text.